A mostly-implemented RISC-V CPU in Verilog.
Features:
- All the basics; 32 registers, 5-stage processor, etc.
- Implemented instructions: loads, stores, load immediates, arithmetic, jumps, calls, branches
- Memory-mapped devices: RAM, UART
Future work:
- Go buy a real FPGA and run it
- Compilation from C
- Pipelining
Based off of the tutorial From Blinker to RISC-V.