Support for SPI4 on STM32F429I-DISCOVERY (#1634)

nanoframework · May 18, 2020 · 7fa7f45 · 7fa7f45
1 parent ecbb0b7
commit 7fa7f45
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Showing 2 changed files with 13 additions and 1 deletion.
diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h
@@ -261,7 +261,7 @@
 #define STM32_SPI_USE_SPI1                  FALSE
 #define STM32_SPI_USE_SPI2                  FALSE
 #define STM32_SPI_USE_SPI3                  FALSE
-#define STM32_SPI_USE_SPI4                  FALSE
+#define STM32_SPI_USE_SPI4                  TRUE
 #define STM32_SPI_USE_SPI5                  TRUE
 #define STM32_SPI_USE_SPI6                  FALSE
 #define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_spi_config.cpp b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_spi_config.cpp
@@ -5,6 +5,18 @@
 
 #include "win_dev_spi_native_target.h"
 
+//////////
+// SPI4 //
+//////////
+
+// pin configuration for SPI4
+// port for SCK pin is: LINE_SPI4_SCK   (=PE2)
+// port for MISO pin is: LINE_SPI4_MISO (=PE5)
+// port for MOSI pin is: LINE_SPI4_MOSI (=PE6)
+
+// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet)
+SPI_CONFIG_PINS(4, GPIOE, 2, GPIOE, 5, GPIOE, 6, 5)
+
 //////////
 // SPI5 //
 //////////