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Improvements in STM32 I2C native implementation
- I2C buffers are now static because of DMA requirements and are configurable at target level - Add I2C configuration files to all I2C enabled targets - I2C transactions are now performed on a working thread to allow CLR execution to move on as the I2C is doing it's thing in background using DMA - Update native declarations of I2C class lib - I2C NativeTransmit now returns an I2cTransferResult object - Update I2C NativeTransmit for ESP32 - Add CLR event for I2C master - Rework CLR events declaration and flags to make it coherent and remove unused one - Add extra comment to CLR_RT_StackFrame::SetupTimeoutFromTicks in order to clarify the need to use a CLR_INT64 argument Signed-off-by: josesimoes <jose.simoes@eclo.solutions>
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34 changes: 34 additions & 0 deletions
34
targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_i2c_config.cpp
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| // | ||
| // Copyright (c) 2018 The nanoFramework project contributors | ||
| // See LICENSE file in the project root for full license information. | ||
| // | ||
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| #include "win_dev_i2c_native.h" | ||
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| ////////// | ||
| // I2C1 // | ||
| ////////// | ||
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| // buffers size | ||
| // tx buffer size (in bytes) | ||
| #define I2C1_WR_SIZE 100 | ||
| // rx buffer size (in bytes) | ||
| #define I2C1_RD_SIZE 100 | ||
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| // buffers declaration | ||
| // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary | ||
| // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C1_WriteBuffer[I2C1_WR_SIZE]; | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C1_ReadBuffer[I2C1_RD_SIZE]; | ||
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| // initialization for I2C1 | ||
| I2C_INIT(1, I2C1_WR_SIZE, I2C1_RD_SIZE) | ||
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| // un-initialization for I2C1 | ||
| I2C_UNINIT(1) |
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34 changes: 34 additions & 0 deletions
34
targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_i2c_config.cpp
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| // | ||
| // Copyright (c) 2018 The nanoFramework project contributors | ||
| // See LICENSE file in the project root for full license information. | ||
| // | ||
|
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| #include "win_dev_i2c_native.h" | ||
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| ////////// | ||
| // I2C1 // | ||
| ////////// | ||
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| // buffers size | ||
| // tx buffer size (in bytes) | ||
| #define I2C1_WR_SIZE 100 | ||
| // rx buffer size (in bytes) | ||
| #define I2C1_RD_SIZE 100 | ||
|
|
||
| // buffers declaration | ||
| // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary | ||
| // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C1_WriteBuffer[I2C1_WR_SIZE]; | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C1_ReadBuffer[I2C1_RD_SIZE]; | ||
|
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| // initialization for I2C1 | ||
| I2C_INIT(1, I2C1_WR_SIZE, I2C1_RD_SIZE) | ||
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| // un-initialization for I2C1 | ||
| I2C_UNINIT(1) |
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62 changes: 62 additions & 0 deletions
62
targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_i2c_config.cpp
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,62 @@ | ||
| // | ||
| // Copyright (c) 2018 The nanoFramework project contributors | ||
| // See LICENSE file in the project root for full license information. | ||
| // | ||
|
|
||
| #include "win_dev_i2c_native.h" | ||
|
|
||
| ////////// | ||
| // I2C1 // | ||
| ////////// | ||
|
|
||
| // buffers size | ||
| // tx buffer size (in bytes) | ||
| #define I2C1_WR_SIZE 100 | ||
| // rx buffer size (in bytes) | ||
| #define I2C1_RD_SIZE 100 | ||
|
|
||
| // buffers declaration | ||
| // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary | ||
| // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C1_WriteBuffer[I2C1_WR_SIZE]; | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C1_ReadBuffer[I2C1_RD_SIZE]; | ||
|
|
||
| // initialization for I2C1 | ||
| I2C_INIT(1, I2C1_WR_SIZE, I2C1_RD_SIZE) | ||
|
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| // un-initialization for I2C1 | ||
| I2C_UNINIT(1) | ||
|
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| ////////// | ||
| // I2C2 // | ||
| ////////// | ||
|
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| // buffers size | ||
| // tx buffer size (in bytes) | ||
| #define I2C2_WR_SIZE 100 | ||
| // rx buffer size (in bytes) | ||
| #define I2C2_RD_SIZE 100 | ||
|
|
||
| // buffers declaration | ||
| // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary | ||
| // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C2_WriteBuffer[I2C2_WR_SIZE]; | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C2_ReadBuffer[I2C2_RD_SIZE]; | ||
|
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| // initialization for I2C2 | ||
| I2C_INIT(2, I2C2_WR_SIZE, I2C2_RD_SIZE) | ||
|
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| // un-initialization for I2C2 | ||
| I2C_UNINIT(2) |
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34 changes: 34 additions & 0 deletions
34
targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_i2c_config.cpp
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| // | ||
| // Copyright (c) 2018 The nanoFramework project contributors | ||
| // See LICENSE file in the project root for full license information. | ||
| // | ||
|
|
||
| #include "win_dev_i2c_native.h" | ||
|
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| ////////// | ||
| // I2C3 // | ||
| ////////// | ||
|
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| // buffers size | ||
| // write buffer size (in bytes) | ||
| #define I2C3_WR_SIZE 100 | ||
| // read buffer size (in bytes) | ||
| #define I2C3_RD_SIZE 100 | ||
|
|
||
| // buffers declaration | ||
| // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary | ||
| // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C3_WriteBuffer[I2C3_WR_SIZE]; | ||
| #if defined(__GNUC__) | ||
| __attribute__((aligned (32))) | ||
| #endif | ||
| uint8_t I2C3_ReadBuffer[I2C3_RD_SIZE]; | ||
|
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| // initialization of I2C3 PAL structure | ||
| I2C_INIT(3, I2C3_WR_SIZE, I2C3_RD_SIZE) | ||
|
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| // un-initialization of I2C3 PAL structure | ||
| I2C_UNINIT(3) |
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