Fixes with declarations for SMT32L0 series (#757)

nanoframework · Jun 22, 2018 · e4bd48f · e4bd48f
1 parent 3af9ac6
commit e4bd48f
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Showing 3 changed files with 23 additions and 33 deletions.
diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h
@@ -69,35 +69,16 @@ typedef struct CRCDriver {
 
 // From STMicroelectronics Cube HAL 
 ///////////////////////////////////////////
-// FIXME
-// THESE can be removed in ChibiOS 18.2
-
-#if defined(STM32F7XX) || defined(STM32H7XX) 
-
-/**
- * @brief   Enables the CRC peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
-
-/**
- * @brief   Disables the CRC peripheral clock.
- *
- * @api
- */
-#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
-
-/**
- * @brief   Resets the CRC peripheral.
- *
- * @api
- */
-#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
-
-#endif //defined(STM32F7XX) || defined(STM32H7XX) 
+
+#if defined(STM32L0XX)
+// this series uses different names for the buses
+
+#define rccEnableCRC(lp) rccEnableAPB1(RCC_AHBENR_CRCEN, lp)
+#define rccDisableCRC() rccDisableAPB1(RCC_AHBENR_CRCEN)
+#define rccResetCRC() rccResetAPB1(RCC_AHB1RSTR_CRCRST)
+
+#endif //defined(STM32L0XX)
+
 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
   * @{
   */

diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c
@@ -70,7 +70,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t timeout)
     //  flag will be set
 
     systime_t start = chVTGetSystemTime();
-    systime_t end = start + MS2ST(timeout);
+    systime_t end = start + TIME_MS2I(timeout);
 
     while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
     { 
@@ -201,8 +201,6 @@ uint8_t flash_lld_getSector(uint32_t address)
 
 int flash_lld_erase(uint32_t address) {
 
-    HAL_StatusTypeDef status = HAL_ERROR;
-
     // unlock the FLASH
     if(HAL_FLASH_Unlock())
     {
@@ -218,7 +216,7 @@ int flash_lld_erase(uint32_t address) {
         *(__IO uint32_t *)(uint32_t)(address & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000;
 
         // Wait for last operation to be completed
-        status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+        FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 
         // If the erase operation is completed, disable the ERASE Bit
         CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);

diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.h
@@ -58,9 +58,20 @@ typedef struct RNGDriver {
 
 // From STMicroelectronics Cube HAL 
 /////////////////////////////////////////////////////////////
+
+#if defined(STM32L0XX)
+// this series uses different names for the buses
+
+#define rccEnableRNG(lp)  rccEnableAPB2(RCC_AHBENR_RNGEN, lp)
+#define rccDisableRNG()   rccDisableAPB2(RCC_AHBENR_RNGEN)
+
+#else
+
 #define rccEnableRNG(lp)  rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
 #define rccDisableRNG()   rccDisableAHB2(RCC_AHB2ENR_RNGEN)
 
+#endif
+
 /*===========================================================================*/
 /* Driver macros.                                                            */
 /*===========================================================================*/