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soc: arm: nxp: ke1xf: use clock nodes for NXP Kinetis SCG clocks
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Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
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@henrikbrixandersen @MaureenHelm
henrikbrixandersen authored and MaureenHelm committed Mar 31, 2021
1 parent 9817058 commit a865b1b
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Showing 6 changed files with 251 additions and 183 deletions.
73 changes: 53 additions & 20 deletions boards/arm/twr_ke18f/twr_ke18f.dts
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
* Copyright (c) 2019-2021 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -128,31 +128,64 @@
};

&scg {
sosc-freq = <8000000>;
sosc-mode = <KINETIS_SCG_SOSC_MODE_LOW_POWER>;
sosc-divider-1 = <1>;
sosc-divider-2 = <1>;

sirc-range = <8000000>;
sirc-divider-1 = <1>;
sirc-divider-2 = <2>;
sosc_clk {
status = "okay";
clock-frequency = <8000000>;
};

pll {
clock-mult = <30>;
};

core_clk {
clocks = <&spll_clk>;
};

bus_clk {
clock-div = <2>;
};

slow_clk {
clock-div = <5>;
};

firc-range = <48000000>;
firc-divider-1 = <1>;
firc-divider-2 = <1>;
clkout_clk {
status = "okay";
};

spll-source = <KINETIS_SCG_SPLL_SRC_SOSC>;
spll-divider-pre = <1>;
spll-multiplier = <30>;
spll-divider-1 = <1>;
spll-divider-2 = <2>;
splldiv1_clk {
clock-div = <1>;
};

clk-source = <KINETIS_SCG_SCLK_SRC_SPLL>;
clk-divider-slow = <5>;
clk-divider-bus = <2>;
clk-divider-core = <1>;
splldiv2_clk {
clock-div = <2>;
};

clkout-source = <KINETIS_SCG_CLKOUT_SRC_FIRC>;
sircdiv1_clk {
clock-div = <1>;
};

sircdiv2_clk {
clock-div = <2>;
};

fircdiv1_clk {
clock-div = <1>;
};

fircdiv2_clk {
clock-div = <1>;
};

soscdiv1_clk {
clock-div = <1>;
};

soscdiv2_clk {
clock-div = <1>;
};
};

&lpuart0 {
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20 changes: 17 additions & 3 deletions drivers/clock_control/clock_control_mcux_scg.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
* Copyright (c) 2019-2021 Vestas Wind Systems A/S
*
* Based on clock_control_mcux_sim.c, which is:
* Copyright (c) 2017, NXP
Expand All @@ -18,6 +18,8 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(clock_control_scg);

#define MCUX_SCG_CLOCK_NODE(name) DT_CHILD(DT_DRV_INST(0), name)

static int mcux_scg_on(const struct device *dev,
clock_control_subsys_t sub_system)
{
Expand Down Expand Up @@ -96,9 +98,21 @@ static int mcux_scg_get_rate(const struct device *dev,

static int mcux_scg_init(const struct device *dev)
{
#if DT_INST_NODE_HAS_PROP(0, clkout_source)
CLOCK_SetClkOutSel(DT_INST_PROP(0, clkout_source));
#if DT_NODE_HAS_STATUS(MCUX_SCG_CLOCK_NODE(clkout_clk), okay)
#if DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(slow_clk))
CLOCK_SetClkOutSel(kClockClkoutSelScgSlow);
#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sosc_clk))
CLOCK_SetClkOutSel(kClockClkoutSelSysOsc);
#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sirc_clk))
CLOCK_SetClkOutSel(kClockClkoutSelSirc);
#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(firc_clk))
CLOCK_SetClkOutSel(kClockClkoutSelFirc);
#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(spll_clk))
CLOCK_SetClkOutSel(kClockClkoutSelSysPll);
#else
#error Unsupported SCG clkout clock source
#endif
#endif /* DT_NODE_HAS_STATUS(MCUX_SCG_CLOCK_NODE(clkout_clk), okay) */

return 0;
}
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119 changes: 118 additions & 1 deletion dts/arm/nxp/nxp_ke1xf.dtsi
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
* Copyright (c) 2019-2021 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand Down Expand Up @@ -100,6 +100,123 @@
reg = <0x40064000 0x1000>;
label = "SCG";
#clock-cells = <1>;

sosc_clk: sosc_clk {
compatible = "fixed-clock";
status = "disabled";
#clock-cells = <0>;
};

sirc_clk: sirc_clk {
compatible = "fixed-clock";
clock-frequency = <8000000>;
#clock-cells = <0>;
};

firc_clk: firc_clk {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};

pll: pll {
compatible = "fixed-factor-clock";
clocks = <&sosc_clk>;
clock-div = <1>;
clock-mult = <16>;
#clock-cells = <0>;
};

spll_clk: spll_clk {
compatible = "fixed-factor-clock";
clocks = <&pll>;
clock-div = <2>;
#clock-cells = <0>;
};

core_clk: core_clk {
compatible = "fixed-factor-clock";
clocks = <&firc_clk>;
clock-div = <1>;
#clock-cells = <0>;
};

bus_clk: bus_clk {
compatible = "fixed-factor-clock";
clocks = <&core_clk>;
clock-div = <1>;
#clock-cells = <0>;
};

slow_clk: slow_clk {
compatible = "fixed-factor-clock";
clocks = <&core_clk>;
clock-div = <2>;
#clock-cells = <0>;
};

clkout_clk: clkout_clk {
compatible = "fixed-factor-clock";
status = "disabled";
clocks = <&firc_clk>;
#clock-cells = <0>;
};

splldiv1_clk: splldiv1_clk {
compatible = "fixed-factor-clock";
clocks = <&spll_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

splldiv2_clk: splldiv2_clk {
compatible = "fixed-factor-clock";
clocks = <&spll_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

sircdiv1_clk: sircdiv1_clk {
compatible = "fixed-factor-clock";
clocks = <&sirc_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

sircdiv2_clk: sircdiv2_clk {
compatible = "fixed-factor-clock";
clocks = <&sirc_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

fircdiv1_clk: fircdiv1_clk {
compatible = "fixed-factor-clock";
clocks = <&firc_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

fircdiv2_clk: fircdiv2_clk {
compatible = "fixed-factor-clock";
clocks = <&firc_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

soscdiv1_clk: soscdiv1_clk {
compatible = "fixed-factor-clock";
clocks = <&sosc_clk>;
clock-div = <0>;
#clock-cells = <0>;
};

soscdiv2_clk: soscdiv2_clk {
compatible = "fixed-factor-clock";
clocks = <&sosc_clk>;
clock-div = <0>;
#clock-cells = <0>;
};
};

pmc: pmc@4007d000 {
Expand Down
97 changes: 1 addition & 96 deletions dts/bindings/arm/nxp,kinetis-scg.yaml
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
# Copyright (c) 2019 Vestas Wind Systems A/S
# Copyright (c) 2019-2021 Vestas Wind Systems A/S
# SPDX-License-Identifier: Apache-2.0

description: NXP Kinetis SCG (System Clock Generator) IP node
Expand All @@ -14,106 +14,11 @@ properties:
label:
required: true

clk-divider-slow:
type: int
description: system clock to slow clock divider
required: true

clk-divider-bus:
type: int
description: system clock to bus clock divider
required: true

clk-divider-core:
type: int
description: system clock to core clock divider
required: true

clk-source:
type: int
description: system clock source
required: false

sosc-freq:
type: int
description: system oscillator (e.g. xtal) frequency
required: false

sosc-mode:
type: int
description: system oscillator mode
required: false

sosc-divider-1:
type: int
description: system oscillator divider 1
required: false

sosc-divider-2:
type: int
description: system oscillator divider 2
required: false

sirc-range:
type: int
description: slow internal reference clock range in MHz
required: true

sirc-divider-1:
type: int
description: slow internal reference clock divider 1
required: true

sirc-divider-2:
type: int
description: slow internal reference clock divider 2
required: true

firc-range:
type: int
description: fast internal reference clock range in MHz
required: true

firc-divider-1:
type: int
description: fast internal reference clock divider 1
required: true

firc-divider-2:
type: int
description: fast internal reference clock divider 2
required: true

spll-source:
type: int
description: system phase-locked loop clock source
required: true

spll-divider-pre:
type: int
description: system phase-locked loop reference clock divider
required: true

spll-multiplier:
type: int
description: system phase-locked loop reference clock multiplier
required: true

spll-divider-1:
type: int
description: system phase-locked loop divider 1
required: true

spll-divider-2:
type: int
description: system phase-locked loop divider 2
required: true

clkout-source:
type: int
description: clockout clock source
required: false

"#clock-cells":
const: 1

Expand Down
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