feat: Introduce new mops for version 2 #321
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This won't reduce many cycles, the benefit is really that AUIPC is historically treated as a basic block end instruction. By eliminating AUIPC, we can expect longer sequential trace that aids execution.
The fixed version is included in version 2, version 1 is left unchanged
The fixed code will be included in version 2.
The fixed code is included in version 2.
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mohanson
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Feb 9, 2023
| ldr TEMP4, REGISTER_ADDRESS(RS2) | ||
| subs TEMP3, TEMP3, TEMP4 | ||
| adc TEMP1, TEMP1, TEMP1 | ||
| eor TEMP1, TEMP1, 1 |
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arm64 uses different borrow logic in subtraction here: when a borrow happened, the carry bit is 0, otherwise the carry bit is 1. This is the opposite of what we want, hence the xor.
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Understand, it is said to simplify chip design
https://stackoverflow.com/questions/53065579/confusion-about-arm-documentation-on-carry-flag
mohanson
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Feb 9, 2023
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| li a0, 1 | ||
| li a7, 93 | ||
| ecall | ||
| 1: | ||
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| ecall |
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These lines are useless, please delete them.
mohanson
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Feb 9, 2023
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This change introduces 5 new mops for ckb-vm version 2. Those new mops all come from a direct observation of generated code from modern LLVM/GCC compilers. While they have less impact on secp256k1 contract(1183580 -> 1148321), they have more significant impact on complicated contracts. Using halo2 as an example: