Implement binary<->text support for SIMD load splats and extends

The names are still pre WebAssembly#297, once that's finalize I can fix this up (after the sync WebAssembly#323). With this change, test/core/run.py passes on all test cases in simd/.
ngzhian · Aug 31, 2020 · 61085bd · 61085bd
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commit 61085bd
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Showing 3 changed files with 61 additions and 7 deletions.
diff --git a/interpreter/binary/decode.ml b/interpreter/binary/decode.ml
@@ -222,6 +222,16 @@ let simd_prefix s =
   let pos = pos s in
   match vu32 s with
   | 0x00l -> let a, o = memop s in v128_load a o
+  | 0x01l -> let a, o = memop s in i16x8_load8x8_s a o
+  | 0x02l -> let a, o = memop s in i16x8_load8x8_u a o
+  | 0x03l -> let a, o = memop s in i32x4_load16x4_s a o
+  | 0x04l -> let a, o = memop s in i32x4_load16x4_u a o
+  | 0x05l -> let a, o = memop s in i64x2_load32x2_s a o
+  | 0x06l -> let a, o = memop s in i64x2_load32x2_u a o
+  | 0x07l -> let a, o = memop s in v8x16_load_splat a o
+  | 0x08l -> let a, o = memop s in v16x8_load_splat a o
+  | 0x09l -> let a, o = memop s in v32x4_load_splat a o
+  | 0x0al -> let a, o = memop s in v64x2_load_splat a o
   | 0x0bl -> let a, o = memop s in v128_store a o
   | 0x0cl -> v128_const (at v128 s)
   | 0x0dl -> v8x16_shuffle (List.init 16 (fun x -> u8 s))

diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml
@@ -197,8 +197,29 @@ let encode m =
         op 0x35; memop mo
       | Load {ty = F32Type | F64Type; sz = Some _; _} ->
         assert false
-      | Load ({ty = V128Type; _} as mo) ->
+
+      | SimdLoad ({ty = V128Type; sz = None; _} as mo) ->
         simd_op 0x00l; memop mo
+      | SimdLoad ({ty = V128Type; sz = Some (Pack64, Pack8x8 SX); _} as mo) ->
+        simd_op 0x01l; memop mo
+      | SimdLoad ({ty = V128Type; sz = Some (Pack64, Pack8x8 ZX); _} as mo) ->
+        simd_op 0x02l; memop mo
+      | SimdLoad ({ty = V128Type; sz = Some (Pack64, Pack16x4 SX); _} as mo) ->
+        simd_op 0x03l; memop mo
+      | SimdLoad ({ty = V128Type; sz = Some (Pack64, Pack16x4 ZX); _} as mo) ->
+        simd_op 0x04l; memop mo
+      | SimdLoad ({ty = V128Type; sz = Some (Pack64, Pack32x2 SX); _} as mo) ->
+        simd_op 0x05l; memop mo
+      | SimdLoad ({ty = V128Type; sz = Some (Pack64, Pack32x2 ZX); _} as mo) ->
+        simd_op 0x06l; memop mo
+      | SimdLoad ({ty= V128Type; sz = Some (Pack8, PackSplat); _} as mo) ->
+        simd_op 0x07l; memop mo
+      | SimdLoad ({ty= V128Type; sz = Some (Pack16, PackSplat); _} as mo) ->
+        simd_op 0x08l; memop mo
+      | SimdLoad ({ty= V128Type; sz = Some (Pack32, PackSplat); _} as mo) ->
+        simd_op 0x09l; memop mo
+      | SimdLoad ({ty= V128Type; sz = Some (Pack64, PackSplat); _} as mo) ->
+        simd_op 0x0al; memop mo
 
       | Store ({ty = I32Type; sz = None; _} as mo) -> op 0x36; memop mo
       | Store ({ty = I64Type; sz = None; _} as mo) -> op 0x37; memop mo
@@ -211,8 +232,8 @@ let encode m =
       | Store ({ty = I64Type; sz = Some Pack16; _} as mo) -> op 0x3d; memop mo
       | Store ({ty = I64Type; sz = Some Pack32; _} as mo) -> op 0x3e; memop mo
       | Store {ty = F32Type | F64Type; sz = Some _; _} -> assert false
-      | Store ({ty = V128Type; _} as mo) ->
-        simd_op 0x0bl; memop mo
+
+      | SimdStore ({ty = V128Type; _} as mo) -> simd_op 0x0bl; memop mo
 
       | MemorySize -> op 0x3f; u8 0x00
       | MemoryGrow -> op 0x40; u8 0x00

diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml
@@ -408,8 +408,9 @@ let relop = oper (IntOp.relop, FloatOp.relop, SimdOp.relop)
 let cvtop = oper (IntOp.cvtop, FloatOp.cvtop, SimdOp.cvtop)
 let ternop = SimdOp.ternop
 
-let memop name {ty; align; offset; _} sz =
-  value_type ty ^ "." ^ name ^
+(* Temporary wart here while we finalize the names of SIMD loads and extends. *)
+let memop ?(type_in_name=true) name {ty; align; offset; _} sz =
+  (if type_in_name then value_type ty ^ "." else "") ^ name ^
   (if offset = 0l then "" else " offset=" ^ nat32 offset) ^
   (if 1 lsl align = sz then "" else " align=" ^ nat (1 lsl align))
 
@@ -419,11 +420,33 @@ let loadop op =
   | Some (sz, ext) ->
     memop ("load" ^ pack_size sz ^ extension ext) op (packed_size sz)
 
+let simd_loadop (op : simd_loadop) =
+  match op.sz with
+  | None -> memop "load" op (size op.ty)
+  | Some (sz, pack_simd) ->
+    let prefix, suffix, ext =
+      (match sz, pack_simd with
+      | Pack64, Pack8x8 ext -> "i16x8", "8x8", extension ext
+      | Pack64, Pack16x4 ext -> "i32x4", "16x4", extension ext
+      | Pack64, Pack32x2 ext -> "i64x2", "32x2", extension ext
+      | Pack8, PackSplat -> "v8x16", "_splat", ""
+      | Pack16, PackSplat -> "v16x8", "_splat", ""
+      | Pack32, PackSplat -> "v32x4", "_splat", ""
+      | Pack64, PackSplat -> "v64x2", "_splat", ""
+      | _ -> assert false
+      ) in
+    memop ~type_in_name:false (prefix ^ ".load" ^ suffix ^ ext) op (packed_size sz)
+
 let storeop op =
   match op.sz with
   | None -> memop "store" op (size op.ty)
   | Some sz -> memop ("store" ^ pack_size sz) op (packed_size sz)
 
+let simd_storeop op =
+  match op.sz with
+  | None -> memop "store" op (size op.ty)
+  | Some _ -> assert false
+
 
 (* Expressions *)
 
@@ -464,8 +487,8 @@ let rec instr e =
     | GlobalGet x -> "global.get " ^ var x, []
     | GlobalSet x -> "global.set " ^ var x, []
     | Load op -> loadop op, []
-    | SimdLoad op -> failwith "unimplemented SimdLoad arrange"
-    | SimdStore op -> failwith "unimplemented SimdStore arrange"
+    | SimdLoad op -> simd_loadop op, []
+    | SimdStore op -> simd_storeop op, []
     | Store op -> storeop op, []
     | MemorySize -> "memory.size", []
     | MemoryGrow -> "memory.grow", []