Specify binary format for SIMD (WebAssembly#333)

ngzhian · Sep 1, 2020 · 71d4fa7 · 71d4fa7
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diff --git a/document/core/binary/conventions.rst b/document/core/binary/conventions.rst
@@ -68,7 +68,8 @@ In order to distinguish symbols of the binary syntax from symbols of the abstrac
        \hex{7F} &\Rightarrow& \I32 \\ &&|&
        \hex{7E} &\Rightarrow& \I64 \\ &&|&
        \hex{7D} &\Rightarrow& \F32 \\ &&|&
-       \hex{7C} &\Rightarrow& \F64 \\
+       \hex{7C} &\Rightarrow& \F64 \\ &&|&
+       \hex{7B} &\Rightarrow& \V128 \\
      \end{array}
 
    Consequently, the byte :math:`\hex{7F}` encodes the type |I32|,

diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst
@@ -403,6 +403,316 @@ whereas the actual opcode is encoded by a variable-length :ref:`unsigned integer
    \end{array}
 
 
+.. index:: simd instruction
+   pair: binary format; instruction
+.. _binary-instr-simd:
+
+SIMD Instructions
+~~~~~~~~~~~~~~~~~~~~
+
+All variants of :ref:`SIMD instructions <syntax-instr-simd>` are represented by separate byte codes.
+The all have a one byte prefix, whereas the actual opcode is encoded by a variable-length :ref:`unsigned integer <binary-uint>`.
+
+SIMD loads and stores are followed by the encoding of their |memarg| immediate.
+
+.. math::
+   \begin{array}{llclll}
+   \production{instruction} & \Binstr &::=& \dots \\&&|&
+     \hex{FD}~~0{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\LOAD~m \\ &&|&
+     \hex{FD}~~1{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I16X8.\LOAD\K{8x8\_s}~m \\ &&|&
+     \hex{FD}~~2{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I16X8.\LOAD\K{8x8\_u}~m \\ &&|&
+     \hex{FD}~~3{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I32X4.\LOAD\K{16x4\_s}~m \\ &&|&
+     \hex{FD}~~4{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I32X4.\LOAD\K{16x4\_u}~m \\ &&|&
+     \hex{FD}~~5{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I64X2.\LOAD\K{32x2\_s}~m \\ &&|&
+     \hex{FD}~~6{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I64X2.\LOAD\K{32x2\_u}~m \\ &&|&
+     \hex{FD}~~7{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I8X16.\LOAD\K{\_splat}~m \\ &&|&
+     \hex{FD}~~8{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I16X8.\LOAD\K{\_splat}~m \\ &&|&
+     \hex{FD}~~9{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I32X4.\LOAD\K{\_splat}~m \\ &&|&
+     \hex{FD}~~10{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \I64X2.\LOAD\K{\_splat}~m \\ &&|&
+     \hex{FD}~~11{:}\Bu32~~m{:}\Bmemarg &\Rightarrow& \V128.\STORE~m \\
+   \end{array}
+
+The |VCONST| instruction is followed by 16 immediate bytes, which are converted into a |i128| in |littleendian| byte order:
+
+.. math::
+   \begin{array}{llclll}
+   \production{instruction} & \Binstr &::=& \dots \\&&|&
+     \hex{FD}~~12{:}\Bu32~~(b{:}\Bbyte)^{16} &\Rightarrow& \V128.\VCONST~
+     bytes_{\K{i128}}^{-1}(b_{0}~\dots~b_{15}) \\
+   \end{array}
+
+.. _binary-vternop:
+
+The |SHUFFLE| instruction is also followed by 16 immediate bytes:
+
+.. math::
+   \begin{array}{llclll}
+   \production{instruction} & \Binstr &::=& \dots \\&&|&
+     \hex{FD}~~13{:}\Bu32~~(b{:}\Bbyte)^{16} &\Rightarrow& \I8X16.\SHUFFLE~b^{16} \\
+   \end{array}
+
+|EXTRACTLANE| and |REPLACELANE| instructions are followed by 1 immediate byte.
+
+.. math::
+   \begin{array}{llclll}
+   \production{instruction} & \Binstr &::=& \dots \\&&|&
+     \hex{FD}~~21{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I8X16.\EXTRACTLANE\K{\_s}~b \\ &&|&
+     \hex{FD}~~22{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I8X16.\EXTRACTLANE\K{\_u}~b \\ &&|&
+     \hex{FD}~~23{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I8X16.\REPLACELANE~b \\ &&|&
+     \hex{FD}~~24{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I16X8.\EXTRACTLANE\K{\_s}~b \\ &&|&
+     \hex{FD}~~25{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I16X8.\EXTRACTLANE\K{\_u}~b \\ &&|&
+     \hex{FD}~~26{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I16X8.\REPLACELANE~b \\ &&|&
+     \hex{FD}~~27{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I32X4.\EXTRACTLANE~b \\ &&|&
+     \hex{FD}~~28{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I32X4.\REPLACELANE~b \\ &&|&
+     \hex{FD}~~29{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I64X2.\EXTRACTLANE~b \\ &&|&
+     \hex{FD}~~30{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \I64X2.\REPLACELANE~b \\ &&|&
+     \hex{FD}~~31{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \F32X4.\EXTRACTLANE~b \\ &&|&
+     \hex{FD}~~32{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \F32X4.\REPLACELANE~b \\ &&|&
+     \hex{FD}~~33{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \F64X2.\EXTRACTLANE~b \\ &&|&
+     \hex{FD}~~34{:}\Bu32~~b{:}\Bbyte &\Rightarrow& \F64X2.\REPLACELANE~b \\
+   \end{array}
+
+All other SIMD instructions are plain opcodes without any immediates.
+
+.. math::
+   \begin{array}{llclll}
+   \production{instruction} & \Binstr &::=& \dots && \phantom{simdhaslongerinstructionnames} \\&&|&
+     \hex{FD}~~14{:}\Bu32 &\Rightarrow& \I8X16.\SWIZZLE \\ &&|&
+     \hex{FD}~~15{:}\Bu32 &\Rightarrow& \I8X16.\SPLAT \\ &&|&
+     \hex{FD}~~16{:}\Bu32 &\Rightarrow& \I16X8.\SPLAT \\ &&|&
+     \hex{FD}~~17{:}\Bu32 &\Rightarrow& \I32X4.\SPLAT \\ &&|&
+     \hex{FD}~~18{:}\Bu32 &\Rightarrow& \I64X2.\SPLAT \\ &&|&
+     \hex{FD}~~19{:}\Bu32 &\Rightarrow& \F32X4.\SPLAT \\ &&|&
+     \hex{FD}~~20{:}\Bu32 &\Rightarrow& \F64X2.\SPLAT \\
+   \end{array}
+
+.. _binary-virelop:
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~35{:}\Bu32 &\Rightarrow& \I8X16.\VEQ \\ &&|&
+     \hex{FD}~~36{:}\Bu32 &\Rightarrow& \I8X16.\VNE \\ &&|&
+     \hex{FD}~~37{:}\Bu32 &\Rightarrow& \I8X16.\VLT\K{\_s} \\ &&|&
+     \hex{FD}~~38{:}\Bu32 &\Rightarrow& \I8X16.\VLT\K{\_u} \\ &&|&
+     \hex{FD}~~39{:}\Bu32 &\Rightarrow& \I8X16.\VGT\K{\_s} \\ &&|&
+     \hex{FD}~~40{:}\Bu32 &\Rightarrow& \I8X16.\VGT\K{\_u} \\ &&|&
+     \hex{FD}~~41{:}\Bu32 &\Rightarrow& \I8X16.\VLE\K{\_s} \\ &&|&
+     \hex{FD}~~42{:}\Bu32 &\Rightarrow& \I8X16.\VLE\K{\_u} \\ &&|&
+     \hex{FD}~~43{:}\Bu32 &\Rightarrow& \I8X16.\VGE\K{\_s} \\ &&|&
+     \hex{FD}~~44{:}\Bu32 &\Rightarrow& \I8X16.\VGE\K{\_u} \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~45{:}\Bu32 &\Rightarrow& \I16X8.\VEQ \\ &&|&
+     \hex{FD}~~46{:}\Bu32 &\Rightarrow& \I16X8.\VNE \\ &&|&
+     \hex{FD}~~47{:}\Bu32 &\Rightarrow& \I16X8.\VLT\K{\_s} \\ &&|&
+     \hex{FD}~~48{:}\Bu32 &\Rightarrow& \I16X8.\VLT\K{\_u} \\ &&|&
+     \hex{FD}~~49{:}\Bu32 &\Rightarrow& \I16X8.\VGT\K{\_s} \\ &&|&
+     \hex{FD}~~50{:}\Bu32 &\Rightarrow& \I16X8.\VGT\K{\_u} \\ &&|&
+     \hex{FD}~~51{:}\Bu32 &\Rightarrow& \I16X8.\VLE\K{\_s} \\ &&|&
+     \hex{FD}~~52{:}\Bu32 &\Rightarrow& \I16X8.\VLE\K{\_u} \\ &&|&
+     \hex{FD}~~53{:}\Bu32 &\Rightarrow& \I16X8.\VGE\K{\_s} \\ &&|&
+     \hex{FD}~~54{:}\Bu32 &\Rightarrow& \I16X8.\VGE\K{\_u} \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~55{:}\Bu32 &\Rightarrow& \I32X4.\VEQ \\ &&|&
+     \hex{FD}~~56{:}\Bu32 &\Rightarrow& \I32X4.\VNE \\ &&|&
+     \hex{FD}~~57{:}\Bu32 &\Rightarrow& \I32X4.\VLT\K{\_s} \\ &&|&
+     \hex{FD}~~58{:}\Bu32 &\Rightarrow& \I32X4.\VLT\K{\_u} \\ &&|&
+     \hex{FD}~~59{:}\Bu32 &\Rightarrow& \I32X4.\VGT\K{\_s} \\ &&|&
+     \hex{FD}~~60{:}\Bu32 &\Rightarrow& \I32X4.\VGT\K{\_u} \\ &&|&
+     \hex{FD}~~61{:}\Bu32 &\Rightarrow& \I32X4.\VLE\K{\_s} \\ &&|&
+     \hex{FD}~~62{:}\Bu32 &\Rightarrow& \I32X4.\VLE\K{\_u} \\ &&|&
+     \hex{FD}~~63{:}\Bu32 &\Rightarrow& \I32X4.\VGE\K{\_s} \\ &&|&
+     \hex{FD}~~64{:}\Bu32 &\Rightarrow& \I32X4.\VGE\K{\_u} \\
+   \end{array}
+
+.. _binary-vfrelop:
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~65{:}\Bu32 &\Rightarrow& \F32X4.\VEQ \\ &&|&
+     \hex{FD}~~66{:}\Bu32 &\Rightarrow& \F32X4.\VNE \\ &&|&
+     \hex{FD}~~67{:}\Bu32 &\Rightarrow& \F32X4.\VLT \\ &&|&
+     \hex{FD}~~68{:}\Bu32 &\Rightarrow& \F32X4.\VGT \\ &&|&
+     \hex{FD}~~69{:}\Bu32 &\Rightarrow& \F32X4.\VLE \\ &&|&
+     \hex{FD}~~70{:}\Bu32 &\Rightarrow& \F32X4.\VGE \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~71{:}\Bu32 &\Rightarrow& \F64X2.\VEQ \\ &&|&
+     \hex{FD}~~72{:}\Bu32 &\Rightarrow& \F64X2.\VNE \\ &&|&
+     \hex{FD}~~73{:}\Bu32 &\Rightarrow& \F64X2.\VLT \\ &&|&
+     \hex{FD}~~74{:}\Bu32 &\Rightarrow& \F64X2.\VGT \\ &&|&
+     \hex{FD}~~75{:}\Bu32 &\Rightarrow& \F64X2.\VLE \\ &&|&
+     \hex{FD}~~76{:}\Bu32 &\Rightarrow& \F64X2.\VGE \\
+   \end{array}
+
+.. _binary-vsunop:
+.. _binary-vsbinop:
+.. _binary-vsternop:
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~77{:}\Bu32 &\Rightarrow& \V128.\VNOT \\ &&|&
+     \hex{FD}~~78{:}\Bu32 &\Rightarrow& \V128.\VAND \\ &&|&
+     \hex{FD}~~79{:}\Bu32 &\Rightarrow& \V128.\VANDNOT \\ &&|&
+     \hex{FD}~~80{:}\Bu32 &\Rightarrow& \V128.\VOR \\ &&|&
+     \hex{FD}~~81{:}\Bu32 &\Rightarrow& \V128.\VXOR \\ &&|&
+     \hex{FD}~~82{:}\Bu32 &\Rightarrow& \V128.\BITSELECT
+   \end{array}
+
+.. _binary-vtestop:
+.. _binary-vshiftop:
+.. _binary-viunop:
+.. _binary-vibinop:
+.. _binary-viminmaxop:
+.. _binary-vsatbinop:
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~96{:}\Bu32 &\Rightarrow& \I8X16.\VABS \\ &&|&
+     \hex{FD}~~97{:}\Bu32 &\Rightarrow& \I8X16.\VNEG \\ &&|&
+     \hex{FD}~~98{:}\Bu32 &\Rightarrow& \I8X16.\ANYTRUE \\ &&|&
+     \hex{FD}~~99{:}\Bu32 &\Rightarrow& \I8X16.\ALLTRUE \\ &&|&
+     \hex{FD}~~100{:}\Bu32 &\Rightarrow& \I8X16.\BITMASK \\ &&|&
+     \hex{FD}~~101{:}\Bu32 &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_s} \\ &&|&
+     \hex{FD}~~102{:}\Bu32 &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_u} \\ &&|&
+     \hex{FD}~~107{:}\Bu32 &\Rightarrow& \I8X16.\VSHL \\ &&|&
+     \hex{FD}~~108{:}\Bu32 &\Rightarrow& \I8X16.\VSHR\K{\_s} \\ &&|&
+     \hex{FD}~~109{:}\Bu32 &\Rightarrow& \I8X16.\VSHR\K{\_u} \\ &&|&
+     \hex{FD}~~110{:}\Bu32 &\Rightarrow& \I8X16.\VADD \\ &&|&
+     \hex{FD}~~111{:}\Bu32 &\Rightarrow& \I8X16.\VADD\K{\_sat\_s} \\ &&|&
+     \hex{FD}~~112{:}\Bu32 &\Rightarrow& \I8X16.\VADD\K{\_sat\_u} \\ &&|&
+     \hex{FD}~~113{:}\Bu32 &\Rightarrow& \I8X16.\VSUB \\ &&|&
+     \hex{FD}~~114{:}\Bu32 &\Rightarrow& \I8X16.\VSUB\K{\_sat\_s} \\ &&|&
+     \hex{FD}~~115{:}\Bu32 &\Rightarrow& \I8X16.\VSUB\K{\_sat\_u} \\ &&|&
+     \hex{FD}~~118{:}\Bu32 &\Rightarrow& \I8X16.\VMIN\K{\_s} \\ &&|&
+     \hex{FD}~~119{:}\Bu32 &\Rightarrow& \I8X16.\VMIN\K{\_u} \\ &&|&
+     \hex{FD}~~120{:}\Bu32 &\Rightarrow& \I8X16.\VMAX\K{\_s} \\ &&|&
+     \hex{FD}~~121{:}\Bu32 &\Rightarrow& \I8X16.\VMAX\K{\_u} \\ &&|&
+     \hex{FD}~~123{:}\Bu32 &\Rightarrow& \I8X16.\AVGR\K{\_u} \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~128{:}\Bu32 &\Rightarrow& \I16X8.\VABS \\ &&|&
+     \hex{FD}~~129{:}\Bu32 &\Rightarrow& \I16X8.\VNEG \\ &&|&
+     \hex{FD}~~130{:}\Bu32 &\Rightarrow& \I16X8.\ANYTRUE \\ &&|&
+     \hex{FD}~~131{:}\Bu32 &\Rightarrow& \I16X8.\ALLTRUE \\ &&|&
+     \hex{FD}~~132{:}\Bu32 &\Rightarrow& \I16X8.\BITMASK \\ &&|&
+     \hex{FD}~~133{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s} \\ &&|&
+     \hex{FD}~~134{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_u} \\ &&|&
+     \hex{FD}~~135{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_s} \\ &&|&
+     \hex{FD}~~136{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_s} \\ &&|&
+     \hex{FD}~~137{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_u} \\ &&|&
+     \hex{FD}~~138{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_u} \\ &&|&
+     \hex{FD}~~139{:}\Bu32 &\Rightarrow& \I16X8.\VSHL \\ &&|&
+     \hex{FD}~~140{:}\Bu32 &\Rightarrow& \I16X8.\VSHR\K{\_s} \\ &&|&
+     \hex{FD}~~141{:}\Bu32 &\Rightarrow& \I16X8.\VSHR\K{\_u} \\ &&|&
+     \hex{FD}~~142{:}\Bu32 &\Rightarrow& \I16X8.\VADD \\ &&|&
+     \hex{FD}~~143{:}\Bu32 &\Rightarrow& \I16X8.\VADD\K{\_sat\_s} \\ &&|&
+     \hex{FD}~~144{:}\Bu32 &\Rightarrow& \I16X8.\VADD\K{\_sat\_u} \\ &&|&
+     \hex{FD}~~145{:}\Bu32 &\Rightarrow& \I16X8.\VSUB \\ &&|&
+     \hex{FD}~~146{:}\Bu32 &\Rightarrow& \I16X8.\VSUB\K{\_sat\_s} \\ &&|&
+     \hex{FD}~~147{:}\Bu32 &\Rightarrow& \I16X8.\VSUB\K{\_sat\_u} \\ &&|&
+     \hex{FD}~~149{:}\Bu32 &\Rightarrow& \I16X8.\VMUL \\ &&|&
+     \hex{FD}~~150{:}\Bu32 &\Rightarrow& \I16X8.\VMIN\K{\_s} \\ &&|&
+     \hex{FD}~~151{:}\Bu32 &\Rightarrow& \I16X8.\VMIN\K{\_u} \\ &&|&
+     \hex{FD}~~152{:}\Bu32 &\Rightarrow& \I16X8.\VMAX\K{\_s} \\ &&|&
+     \hex{FD}~~153{:}\Bu32 &\Rightarrow& \I16X8.\VMAX\K{\_u} \\ &&|&
+     \hex{FD}~~155{:}\Bu32 &\Rightarrow& \I16X8.\AVGR\K{\_u} \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~160{:}\Bu32 &\Rightarrow& \I32X4.\VABS \\ &&|&
+     \hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|&
+     \hex{FD}~~162{:}\Bu32 &\Rightarrow& \I32X4.\ANYTRUE \\ &&|&
+     \hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|&
+     \hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|&
+     \hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s} \\ &&|&
+     \hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s} \\ &&|&
+     \hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u} \\ &&|&
+     \hex{FD}~~170{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u} \\ &&|&
+     \hex{FD}~~171{:}\Bu32 &\Rightarrow& \I32X4.\VSHL \\ &&|&
+     \hex{FD}~~172{:}\Bu32 &\Rightarrow& \I32X4.\VSHR\K{\_s} \\ &&|&
+     \hex{FD}~~173{:}\Bu32 &\Rightarrow& \I32X4.\VSHR\K{\_u} \\ &&|&
+     \hex{FD}~~174{:}\Bu32 &\Rightarrow& \I32X4.\VADD \\ &&|&
+     \hex{FD}~~177{:}\Bu32 &\Rightarrow& \I32X4.\VSUB \\ &&|&
+     \hex{FD}~~181{:}\Bu32 &\Rightarrow& \I32X4.\VMUL \\ &&|&
+     \hex{FD}~~182{:}\Bu32 &\Rightarrow& \I32X4.\VMIN\K{\_s} \\ &&|&
+     \hex{FD}~~183{:}\Bu32 &\Rightarrow& \I32X4.\VMIN\K{\_u} \\ &&|&
+     \hex{FD}~~184{:}\Bu32 &\Rightarrow& \I32X4.\VMAX\K{\_s} \\ &&|&
+     \hex{FD}~~185{:}\Bu32 &\Rightarrow& \I32X4.\VMAX\K{\_u} \\
+  \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
+     \hex{FD}~~203{:}\Bu32 &\Rightarrow& \I64X2.\VSHL \\ &&|&
+     \hex{FD}~~204{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_s} \\ &&|&
+     \hex{FD}~~205{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_u} \\ &&|&
+     \hex{FD}~~206{:}\Bu32 &\Rightarrow& \I64X2.\VADD \\ &&|&
+     \hex{FD}~~209{:}\Bu32 &\Rightarrow& \I64X2.\VSUB \\ &&|&
+     \hex{FD}~~213{:}\Bu32 &\Rightarrow& \I64X2.\VMUL \\
+  \end{array}
+
+.. _binary-vfunop:
+.. _binary-vfbinop:
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~224{:}\Bu32 &\Rightarrow& \F32X4.\VABS \\ &&|&
+     \hex{FD}~~225{:}\Bu32 &\Rightarrow& \F32X4.\VNEG \\ &&|&
+     \hex{FD}~~227{:}\Bu32 &\Rightarrow& \F32X4.\VSQRT \\ &&|&
+     \hex{FD}~~228{:}\Bu32 &\Rightarrow& \F32X4.\VADD \\ &&|&
+     \hex{FD}~~229{:}\Bu32 &\Rightarrow& \F32X4.\VSUB \\ &&|&
+     \hex{FD}~~230{:}\Bu32 &\Rightarrow& \F32X4.\VMUL \\ &&|&
+     \hex{FD}~~231{:}\Bu32 &\Rightarrow& \F32X4.\VDIV \\ &&|&
+     \hex{FD}~~232{:}\Bu32 &\Rightarrow& \F32X4.\VMIN \\ &&|&
+     \hex{FD}~~233{:}\Bu32 &\Rightarrow& \F32X4.\VMAX \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~236{:}\Bu32 &\Rightarrow& \F64X2.\VABS \\ &&|&
+     \hex{FD}~~237{:}\Bu32 &\Rightarrow& \F64X2.\VNEG \\ &&|&
+     \hex{FD}~~239{:}\Bu32 &\Rightarrow& \F64X2.\VSQRT \\ &&|&
+     \hex{FD}~~240{:}\Bu32 &\Rightarrow& \F64X2.\VADD \\ &&|&
+     \hex{FD}~~241{:}\Bu32 &\Rightarrow& \F64X2.\VSUB \\ &&|&
+     \hex{FD}~~242{:}\Bu32 &\Rightarrow& \F64X2.\VMUL \\ &&|&
+     \hex{FD}~~243{:}\Bu32 &\Rightarrow& \F64X2.\VDIV \\ &&|&
+     \hex{FD}~~244{:}\Bu32 &\Rightarrow& \F64X2.\VMIN \\ &&|&
+     \hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VMAX \\
+   \end{array}
+
+.. math::
+   \begin{array}{llclll}
+   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~248{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_s} \\ &&|&
+     \hex{FD}~~249{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_u} \\ &&|&
+     \hex{FD}~~250{:}\Bu32 &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_s} \\ &&|&
+     \hex{FD}~~251{:}\Bu32 &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_u} \\
+   \end{array}
+
+
 .. index:: expression
    pair: binary format; expression
    single: expression; constant

diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst
@@ -247,8 +247,8 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
      \K{i16x8.}\K{mul} ~|~
      \K{i32x4.}\K{mul} ~|~
      \K{i64x2.}\K{mul} \\&&|&
-     \K{i8x16.}\AVGRU ~|~
-     \K{i16x8.}\AVGRU \\&&|&
+     \K{i8x16.}\AVGR\K{\_u} ~|~
+     \K{i16x8.}\AVGR\K{\_u} \\&&|&
      \X{fxx.}\vfbinop \\&&|&
      \K{i32x4.}\TRUNC\K{\_sat\_f32x4\_}\sx ~|~
      \K{f32x4.}\CONVERT\K{\_i32x4\_}\sx \\&&|&