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Failure running conv2d i32 with objectFifo #619
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@jtuyls something new introduced here. Our conv tiling creates interleaved L2->L1 copies with compute:
This is new compared to current matmul, where Question: should the insert-cores op should turn this into code like
i.e. should we duplicate loop structure for dma_cpy_nps and the core ? (with the consumer/producer stuff inserted as usual too) |
Update: probably need some sort of loop subsumption. Hoisting the dma_cpy_nd ops out of the scf.for loops |
This PR switches all numerical convolution tests to use the objectFifo pipeline. With respect to the new tiling strategy: 1) A single **column** is currently used. Targeting multiple columns results in ` error: 'aie.memtile_dma' op could not find and assign a valid BD id`. This will will be investigated as follow-up work: #821 2) There is no longer interleaving of compute and L2->L1 data movement, which means #619 becomes low priority / obsolete 3) L3->L2, L2->L3 still uses padding. But L2->L1, L1->L2 uses packing. 4) Channel-first convolution is completely unsupported, we expect high level transforms to convert to channel last before reaching our backend. 5) Vectorization is not currently enabled, due to issues with alignment. See follow-up task #820. This is functionally ok for now, as peano can scalarize code for all data types.
Checkpoints in IR:
IR Dump Before AssignTargetDevicesPass
IR Dump Before FoldMemRefAliasOps
IR Dump Before AMDAIENormalizeLoopBounds
IR Dump Before AMDAIEInsertCores
Core dumped in AMDAIEInsertCores.
first_run_conv.txt
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