[AssignTiles][CI] Fix assign-tiles for L3 buffers with multiple tile candidate + add e2e test targeting 4x8 AIE array on Strix #1031
+369
−6
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Abhishek-Varma
force-pushed
the
avarma_same_tile_assg_multi_col
branch
from
49d1660 to
defa226
Compare
jtuyls
reviewed
Jan 17, 2025
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Outdated
Show resolved
Hide resolved
jtuyls
reviewed
Jan 17, 2025
.../plugins/target/AMD-AIE/iree-amd-aie/Transforms/Utils/AMDAIELogicalObjFifoSplittingUtils.cpp
Outdated
Show resolved
Hide resolved
Abhishek-Varma
force-pushed
the
avarma_same_tile_assg_multi_col
branch
from
defa226 to
f1c2085
Compare
Abhishek-Varma
changed the base branch from
main
to
avarma_use_gcd_for_split_factor
…iff block -- Required to enable 4x8 AIE array on Strix. -- Before this commit `iree-amdaie-assign-tiles` pass will end up allocating/distributing LHS L3 buffers on (0,0) -> (7,0). -- Since this leads to consumer DMA channel exhaustion later on, this commit aims to address the same and tries to assign same tile set to L3 buffers on different block. -- As a result, we will get LHS L3 buffers on (0,0) -> (4,0). Signed-off-by: Abhishek Varma <abhvarma@amd.com>
-- Adds e2e Matmul 1024x1204x1024 i32 test for 4x8 AIE array on Strix. Signed-off-by: Abhishek Varma <abhvarma@amd.com>
Abhishek-Varma
force-pushed
the
avarma_same_tile_assg_multi_col
branch
2 times, most recently
from
9629558 to
6e9d1f8
Compare
Abhishek-Varma
force-pushed
the
avarma_same_tile_assg_multi_col
branch
from
6e9d1f8 to
c86ba72
Compare
Abhishek-Varma
requested review from
MaheshRavishankar,
nirvedhmeshram and
yzhang93
as code owners
jtuyls
requested changes
Jan 21, 2025
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Outdated
Show resolved
Hide resolved
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Show resolved
Hide resolved
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Outdated
Show resolved
Hide resolved
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Outdated
Show resolved
Hide resolved
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/test/assign_tiles.mlir
Show resolved
Hide resolved
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Outdated
Show resolved
Hide resolved
jtuyls
approved these changes
Jan 22, 2025
compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEAssignTiles.cpp
Show resolved
Hide resolved
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR logically contains two commits :-
Commit 1
-- Required to enable 4x8 AIE array on Strix.
-- Before this commit
iree-amdaie-assign-tilespass ends up allocating/distributing LHS L3 buffers on (0,0) -> (7,0).-- Since this leads to consumer DMA channel exhaustion later on, this commit aims to address the same and tries to assign same tile set to L3 buffers based on the L3 LOF count for L3<->L2 Copy.
Commit 2
-- Updates
mm_npu4.ccfor targeting 4x8 intrinsic for ukernel.-- Adds two e2e tests for CI : a normal execution and a ukernel based execution.
Signed-off-by: Abhishek Varma abhvarma@amd.com