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feat(ssa): Merge slices in if statements with witness conditions (#2347)
Co-authored-by: jfecher <jake@aztecprotocol.com>
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crates/nargo_cli/tests/compile_failure/slice_access_failure/Nargo.toml
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[package] | ||
name = "slice_access_failure" | ||
type = "bin" | ||
authors = [""] | ||
compiler_version = "0.10.2" | ||
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[dependencies] |
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crates/nargo_cli/tests/compile_failure/slice_access_failure/Prover.toml
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x = "5" | ||
y = "10" |
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crates/nargo_cli/tests/compile_failure/slice_access_failure/src/main.nr
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fn main(x : Field, y : pub Field) { | ||
let mut slice = [0; 2]; | ||
if x == y { | ||
slice = slice.push_back(y); | ||
slice = slice.push_back(x); | ||
} else { | ||
slice = slice.push_back(x); | ||
} | ||
// This constraint should fail as the slice length is 3 and the index is 3 | ||
// The right hand side AND case ensures that the circuit inputs have not changed | ||
// and we always hit the else case in the if statement above. | ||
assert((slice[3] == 0) & (slice[2] != y)); | ||
} |
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