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Addressed in Address GtEq extra opcodes #1444
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kevaundray committed May 30, 2023
1 parent b935436 commit 7d8753b
Showing 1 changed file with 0 additions and 7 deletions.
7 changes: 0 additions & 7 deletions crates/noirc_evaluator/src/ssa_refactor/acir_gen/mod.rs
Original file line number Diff line number Diff line change
@@ -173,13 +173,6 @@ impl Context {
// Note: that this produces unnecessary constraints when
// this Eq instruction is being used for a constrain statement
BinaryOp::Eq => self.acir_context.eq_var(lhs, rhs),
// TODO: This is going to be somewhat inefficient initially since
// TODO: ACIR generates constraint using more_than_eq and then adds
// TODO: an opcode to switch it to less than, whereas
// TODO: SSA IR adds an instruction to do less_than
// TODO and then adds a not instruction to make it more_than_eq
// TODO: We can handle this on the ACIR side by adding an optimization
// TODO: though perhaps we can just switch SSA IR to use MoreThanEq?
BinaryOp::Lt => self
.acir_context
.less_than_var(lhs, rhs)

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