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fix: don't range constrain results of unconstrained entrypoint
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TomAFrench committed Feb 7, 2024
1 parent fd15052 commit faed734
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Showing 2 changed files with 12 additions and 5 deletions.
14 changes: 10 additions & 4 deletions compiler/noirc_evaluator/src/ssa/acir_gen/acir_ir/acir_variable.rs
Original file line number Diff line number Diff line change
Expand Up @@ -319,6 +319,7 @@ impl AcirContext {
vec![AcirValue::Var(var, AcirType::field())],
vec![AcirType::field()],
true,
false,
)?;
let inverted_var = Self::expect_one_var(results);

Expand Down Expand Up @@ -706,6 +707,7 @@ impl AcirContext {
],
vec![AcirType::unsigned(max_q_bits), AcirType::unsigned(max_rhs_bits)],
true,
false,
)?
.try_into()
.expect("quotient only returns two values");
Expand Down Expand Up @@ -1438,6 +1440,7 @@ impl AcirContext {
inputs: Vec<AcirValue>,
outputs: Vec<AcirType>,
attempt_execution: bool,
unsafe_return_values: bool,
) -> Result<Vec<AcirValue>, RuntimeError> {
let b_inputs = try_vecmap(inputs, |i| -> Result<_, InternalError> {
match i {
Expand Down Expand Up @@ -1511,11 +1514,14 @@ impl AcirContext {
}
Ok(())
}

for output_var in &outputs_var {
range_constraint_value(self, output_var)?;

// This is a hack to ensure that if we're compiling a brillig entrypoint function then
// we don't also add a number of range constraints.
if !unsafe_return_values {
for output_var in &outputs_var {
range_constraint_value(self, output_var)?;
}
}

Ok(outputs_var)
}

Expand Down
3 changes: 2 additions & 1 deletion compiler/noirc_evaluator/src/ssa/acir_gen/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -270,6 +270,7 @@ impl Context {
inputs,
outputs,
false,
true,
)?;
let output_vars: Vec<_> = output_values
.iter()
Expand Down Expand Up @@ -523,7 +524,7 @@ impl Context {

let outputs: Vec<AcirType> = vecmap(result_ids, |result_id| dfg.type_of_value(*result_id).into());

let output_values = self.acir_context.brillig(self.current_side_effects_enabled_var, code, inputs, outputs, true)?;
let output_values = self.acir_context.brillig(self.current_side_effects_enabled_var, code, inputs, outputs, true, false)?;

// Compiler sanity check
assert_eq!(result_ids.len(), output_values.len(), "ICE: The number of Brillig output values should match the result ids in SSA");
Expand Down

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