feat(brillig): foreign calls with dynamic-size objects

Cargo.toml

@@ -24,7 +24,7 @@ edition = "2021"
 rust-version = "1.66"
 
 [workspace.dependencies]
-acvm = "0.15.0"
+acvm = "0.15.1"
 arena = { path = "crates/arena" }
 fm = { path = "crates/fm" }
 iter-extended = { path = "crates/iter-extended" }

crates/nargo/src/ops/execute.rs

@@ -1,4 +1,3 @@
-use acvm::acir::brillig_vm::ForeignCallResult;
 use acvm::acir::circuit::Opcode;
 use acvm::pwg::{solve, Blocks, PartialWitnessGeneratorStatus, UnresolvedBrilligCall};
 use acvm::PartialWitnessGenerator;
@@ -34,9 +33,7 @@ pub fn execute_circuit(
             if foreign_call_wait_info.function == "oracle_print_impl" {
                 let values = &foreign_call_wait_info.inputs[0];
                 println!("{:?}", values[0].to_field().to_hex());
-                brillig.foreign_call_results.push(ForeignCallResult {
-                    values: vec![vec![foreign_call_wait_info.inputs[0][0]]],
-                });
+                brillig.foreign_call_results.push(foreign_call_wait_info.inputs[0][0].into());
             } else if foreign_call_wait_info.function == "oracle_print_array_impl" {
                 let mut outputs_hex = Vec::new();
                 for value in foreign_call_wait_info.inputs.clone() {
@@ -46,9 +43,7 @@ pub fn execute_circuit(
                 let comma_separated_elements = outputs_hex.join(", ");
                 let output_witnesses_string = "[".to_owned() + &comma_separated_elements + "]";
                 println!("{output_witnesses_string}");
-                brillig.foreign_call_results.push(ForeignCallResult {
-                    values: vec![vec![foreign_call_wait_info.inputs[0][0]]],
-                });
+                brillig.foreign_call_results.push(foreign_call_wait_info.inputs[0][0].into());
             }
 
             let mut next_opcodes_for_solving = vec![Opcode::Brillig(brillig)];

crates/nargo_cli/tests/test_data_ssa_refactor/brillig_oracle/src/main.nr

@@ -21,4 +21,3 @@ unconstrained fn oracle_print_array_wrapper(arr: [Field; 2]) {
     oracle_print_array(arr);
 }
 
-

crates/noirc_evaluator/src/brillig/brillig_gen/brillig_block.rs

@@ -10,7 +10,7 @@ use crate::ssa_refactor::ir::{
     types::{NumericType, Type},
     value::{Value, ValueId},
 };
-use acvm::acir::brillig_vm::{BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterValueOrArray};
+use acvm::acir::brillig_vm::{BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterOrMemory};
 use acvm::FieldElement;
 use iter_extended::vecmap;
 
@@ -430,12 +430,12 @@ impl<'block> BrilligBlock<'block> {
         &mut self,
         value_id: ValueId,
         dfg: &DataFlowGraph,
-    ) -> RegisterValueOrArray {
+    ) -> RegisterOrMemory {
         let register_index = self.convert_ssa_value(value_id, dfg);
         let typ = dfg[value_id].get_type();
         match typ {
-            Type::Numeric(_) => RegisterValueOrArray::RegisterIndex(register_index),
-            Type::Array(_, size) => RegisterValueOrArray::HeapArray(register_index, size),
+            Type::Numeric(_) => RegisterOrMemory::RegisterIndex(register_index),
+            Type::Array(_, size) => RegisterOrMemory::HeapArray(register_index, size),
             _ => {
                 unreachable!("type not supported for conversion into brillig register")
             }

crates/noirc_evaluator/src/brillig/brillig_ir.rs

@@ -14,8 +14,7 @@ use self::{
 };
 use acvm::{
     acir::brillig_vm::{
-        BinaryFieldOp, BinaryIntOp, Opcode as BrilligOpcode, RegisterIndex, RegisterValueOrArray,
-        Value,
+        BinaryFieldOp, BinaryIntOp, Opcode as BrilligOpcode, RegisterIndex, RegisterOrMemory, Value,
     },
     FieldElement,
 };
@@ -339,7 +338,6 @@ impl BrilligContext {
     /// the VM.
     pub(crate) fn return_instruction(&mut self, return_registers: &[RegisterIndex]) {
         debug_show::return_instruction(return_registers);
-
         let mut sources = Vec::with_capacity(return_registers.len());
         let mut destinations = Vec::with_capacity(return_registers.len());
 
@@ -442,11 +440,10 @@ impl BrilligContext {
     pub(crate) fn foreign_call_instruction(
         &mut self,
         func_name: String,
-        inputs: &[RegisterValueOrArray],
-        outputs: &[RegisterValueOrArray],
+        inputs: &[RegisterOrMemory],
+        outputs: &[RegisterOrMemory],
     ) {
         debug_show::foreign_call_instruction(func_name.clone(), inputs, outputs);
-        // TODO(https://github.com/noir-lang/acvm/issues/366): Enable multiple inputs and outputs to a foreign call
         let opcode = BrilligOpcode::ForeignCall {
             function: func_name,
             destinations: outputs.to_vec(),
@@ -592,7 +589,9 @@ impl BrilligContext {
     }
 
     /// Adds a unresolved external `Call` instruction to the bytecode.
+    /// This calls into another function compiled into this brillig artifact.
     pub(crate) fn add_external_call_instruction<T: ToString>(&mut self, func_label: T) {
+        debug_show::add_external_call_instruction(func_label.to_string());
         self.obj.add_unresolved_external_call(
             BrilligOpcode::Call { location: 0 },
             func_label.to_string(),
@@ -702,3 +701,86 @@ pub(crate) enum BrilligBinaryOp {
     // Brillig.
     Modulo { is_signed_integer: bool, bit_size: u32 },
 }
+
+#[cfg(test)]
+mod tests {
+    use std::vec;
+
+    use acvm::acir::brillig_vm::{
+        BinaryIntOp, ForeignCallOutput, ForeignCallResult, RegisterIndex, RegisterOrMemory,
+        Registers, VMStatus, Value, VM,
+    };
+
+    use crate::brillig::brillig_ir::{BrilligContext, BRILLIG_MEMORY_ADDRESSING_BIT_SIZE};
+
+    use super::{BrilligBinaryOp, BrilligOpcode, ReservedRegisters};
+
+    /// Test a Brillig foreign call returning a vector
+    #[test]
+    fn test_brillig_ir_foreign_call_return_vector() {
+        // pseudo-noir:
+        //
+        // #[oracle(make_number_sequence)]
+        // unconstrained fn make_number_sequence(size: u32) -> Vec<u32> {
+        // }
+        //
+        // unconstrained fn main() -> Vec<u32> {
+        //   let the_sequence = make_number_sequence(12);
+        //   assert(the_sequence.len() == 12);
+        // }
+        let mut context = BrilligContext::new(vec![], vec![]);
+        let r_stack = ReservedRegisters::stack_pointer();
+        // Start stack pointer at 0
+        context.const_instruction(r_stack, Value::from(0_usize));
+        let r_input_size = RegisterIndex::from(ReservedRegisters::len());
+        let r_array_ptr = RegisterIndex::from(ReservedRegisters::len() + 1);
+        let r_output_size = RegisterIndex::from(ReservedRegisters::len() + 2);
+        let r_equality = RegisterIndex::from(ReservedRegisters::len() + 3);
+        context.const_instruction(r_input_size, Value::from(12_usize));
+        // copy our stack frame to r_array_ptr
+        context.mov_instruction(r_array_ptr, r_stack);
+        context.foreign_call_instruction(
+            "make_number_sequence".into(),
+            &[RegisterOrMemory::RegisterIndex(r_input_size)],
+            &[RegisterOrMemory::HeapVector(r_stack, r_output_size)],
+        );
+        // push stack frame by r_returned_size
+        context.binary_instruction(
+            r_stack,
+            r_output_size,
+            r_stack,
+            BrilligBinaryOp::Integer {
+                op: BinaryIntOp::Add,
+                bit_size: BRILLIG_MEMORY_ADDRESSING_BIT_SIZE,
+            },
+        );
+        // check r_input_size == r_output_size
+        context.binary_instruction(
+            r_input_size,
+            r_output_size,
+            r_equality,
+            BrilligBinaryOp::Integer {
+                op: BinaryIntOp::Equals,
+                bit_size: BRILLIG_MEMORY_ADDRESSING_BIT_SIZE,
+            },
+        );
+        // We push a JumpIf and Trap opcode directly as the constrain instruction
+        // uses unresolved jumps which requires a block to be constructed in SSA and
+        // we don't need this for Brillig IR tests
+        context.push_opcode(BrilligOpcode::JumpIf { condition: r_equality, location: 8 });
+        context.push_opcode(BrilligOpcode::Trap);
+
+        context.stop_instruction();
+
+        let bytecode = context.artifact().byte_code;
+        let number_sequence: Vec<Value> = (0_usize..12_usize).map(Value::from).collect();
+        let mut vm = VM::new(
+            Registers { inner: vec![] },
+            vec![],
+            bytecode,
+            vec![ForeignCallResult { values: vec![ForeignCallOutput::Array(number_sequence)] }],
+        );
+        let status = vm.process_opcodes();
+        assert_eq!(status, VMStatus::Finished);
+    }
+}

crates/noirc_evaluator/src/brillig/brillig_ir/debug_show.rs

@@ -1,9 +1,7 @@
 ///! This module contains functions for producing a higher level view disassembler of Brillig.
 use super::BrilligBinaryOp;
 use crate::brillig::brillig_ir::{ReservedRegisters, BRILLIG_MEMORY_ADDRESSING_BIT_SIZE};
-use acvm::acir::brillig_vm::{
-    BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterValueOrArray, Value,
-};
+use acvm::acir::brillig_vm::{BinaryFieldOp, BinaryIntOp, RegisterIndex, RegisterOrMemory, Value};
 
 /// Controls whether debug traces are enabled
 const ENABLE_DEBUG_TRACE: bool = true;
@@ -98,13 +96,16 @@ impl DebugToString for Value {
     }
 }
 
-impl DebugToString for RegisterValueOrArray {
+impl DebugToString for RegisterOrMemory {
     fn debug_to_string(&self) -> String {
         match self {
-            RegisterValueOrArray::RegisterIndex(index) => index.debug_to_string(),
-            RegisterValueOrArray::HeapArray(index, size) => {
+            RegisterOrMemory::RegisterIndex(index) => index.debug_to_string(),
+            RegisterOrMemory::HeapArray(index, size) => {
                 format!("{}[0..{}]", index.debug_to_string(), size)
             }
+            RegisterOrMemory::HeapVector(index, size_register) => {
+                format!("{}[0..*{}]", index.debug_to_string(), size_register.debug_to_string())
+            }
         }
     }
 }
@@ -116,14 +117,14 @@ impl<T: DebugToString> DebugToString for [T] {
 }
 
 macro_rules! debug_println {
-    ( $first:expr ) => {
+    ( $literal:expr ) => {
         if ENABLE_DEBUG_TRACE {
-            println!("{}", $first);
+            println!("{}", $literal);
         }
     };
-    ( $first:expr, $( $x:expr ),* ) => {
+    ( $format_message:expr, $( $x:expr ),* ) => {
         if ENABLE_DEBUG_TRACE {
-            println!($first, $( $x.debug_to_string(), )*)
+            println!($format_message, $( $x.debug_to_string(), )*)
         }
     };
 }
@@ -167,14 +168,14 @@ pub(crate) fn const_instruction(result: RegisterIndex, constant: Value) {
 
 /// Processes a not instruction. Append with "_" as this is a high-level instruction.
 pub(crate) fn not_instruction(condition: RegisterIndex, result: RegisterIndex) {
-    debug_println!("  _NOT {} = !{}", result, condition);
+    debug_println!("  NOT {} = !{}", result, condition);
 }
 
 /// Processes a foreign call instruction.
 pub(crate) fn foreign_call_instruction(
     func_name: String,
-    inputs: &[RegisterValueOrArray],
-    outputs: &[RegisterValueOrArray],
+    inputs: &[RegisterOrMemory],
+    outputs: &[RegisterOrMemory],
 ) {
     debug_println!("  FOREIGN_CALL {} ({}) => {}", func_name, inputs, outputs);
 }
@@ -252,3 +253,8 @@ pub(crate) fn cast_instruction(
 ) {
     debug_println!("  CAST {} FROM {} TO {} BITS", destination, source, target_bit_size);
 }
+
+/// Debug function for cast_instruction
+pub(crate) fn add_external_call_instruction(func_label: String) {
+    debug_println!("  CALL {}", func_label);
+}