fix: SSA typing for right shifts

[sirasistant]

Description

Problem*

Partial work towards #4275

Summary*

Previously, SSA was issuing (lhs_type, Field) DIV for right shifts. However this is wrong if we support shifts by the bit size (u1 >> 1)

This is interpreted in acir_gen as an euclidean division with bit_size = lhs_type.bit_size(). However, u1 >> 1 worked because of a + 1 that is in euclidean division

noir/compiler/noirc_evaluator/src/ssa/acir_gen/acir_ir/acir_variable.rs

Line 703 in 0e07303

brillig_directive::directive_quotient(bit_size + 1),

(and it failed in unconstrained functions since they don't codegen that extraneous + 1)

Additional Context

Documentation*

Check one:

• No documentation needed.
• Documentation included in this PR.
• [Exceptional Case] Documentation to be submitted in a separate PR.

PR Checklist*

• I have tested the changes locally.
• I have formatted the changes with Prettier and/or cargo fmt on default settings.

[github-actions]

Changes to circuit sizes

Generated at commit: 7d444a7e28e952c421c53b17f5f8b600f4183788, compared to commit: 0e073037b00212fd17fc8ca9c531b567614eb4c5

🧾 Summary (10% most significant diffs)

Program	ACIR opcodes (+/-)	%	Circuit size (+/-)	%
bit_shifts_runtime	+487 ❌	+21.13%	+482 ❌	+8.99%
simple_shift_left_right	0 ➖	0.00%	+174 ❌	+5.84%

---

Full diff report 👇

Program	ACIR opcodes (+/-)	%	Circuit size (+/-)	%
bit_shifts_runtime	2,792 (+487)	+21.13%	5,844 (+482)	+8.99%
simple_shift_left_right	14 (0)	0.00%	3,155 (+174)	+5.84%
sha2_byte	39,681 (0)	0.00%	153,305 (+37)	+0.02%

[TomAFrench]

Looking at the changes to simple_shift_left_right, ssa changes

Before
acir fn main f0 {
  b0(v0: u32):
    v31 = div v0, Field 2⁴
    v32 = mul v0, u32 2⁴
    v33 = truncate v32 to 32 bits, max_bit_size: 36
    v34 = div v33, Field 2⁸
    constrain v31 == v34
    return 
}


After
acir fn main f0 {
  b0(v0: u32):
    v51 = cast v0 as u33
    v52 = div v51, u33 2⁴
    v53 = cast v52 as u32
    v54 = mul v0, u32 2⁴
    v55 = truncate v54 to 32 bits, max_bit_size: 36
    v56 = cast v55 as u33
    v57 = div v56, u33 2⁸
    v58 = cast v57 as u32
    constrain v53 == v58
    return 
}

These additional casts are preventing us from doing some SSA optimisations. Not a blocker for this PR however we should look at whether we can look through these casts to recover some performance.

[TomAFrench]

Gonna take a couple of mins to see if we can fix this in this PR, will approve in a sec

[TomAFrench]

Doesn't seem like there's a clean way to handle this without turning this PR into a wider SSA optimisation PR.