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fix: Ensure that destination register is allocated when moving between registers in brillig gen #4316

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merged 1 commit into from
Feb 9, 2024
Merged

fix: Ensure that destination register is allocated when moving between registers in brillig gen #4316

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5 changes: 4 additions & 1 deletion compiler/noirc_evaluator/src/brillig/brillig_ir.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -916,8 +916,11 @@ impl BrilligContext {
//
// This means that the arguments will be in the first `n` registers after
// the number of reserved registers.
let (sources, destinations) =
let (sources, destinations): (Vec<_>, Vec<_>) =
arguments.iter().enumerate().map(|(i, argument)| (*argument, self.register(i))).unzip();
destinations
.iter()
.for_each(|destination| self.registers.ensure_register_is_allocated(*destination));
self.mov_registers_to_registers_instruction(sources, destinations);
saved_registers
}
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3 changes: 1 addition & 2 deletions tooling/debugger/ignored-tests.txt
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Expand Up @@ -16,5 +16,4 @@ scalar_mul
signed_comparison
simple_2d_array
to_bytes_integration
bigint
brillig_slices
bigint
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