Testing/tau #4
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CONFIG_MTD is necessary for using SPI flash in 2024.04 u-boot. Some defconfigs missed to enable it when flexspi nor is enabled. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT and IMX8MP_CLK_MEDIA_DISP2_PIX to CCM clock tree to avoid media_blk_ctrl assigned clock parents failure. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
U-boot uses fixed VIDEO_PLL 594Mhz and 27Mhz DSI PHY PLL. remove the assigned-clock-rates for VIDEO_PLL from DTS, because it sets to different rate and causes display issue. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
num_image_type_guids is decrepated, num_images should be used, otherwise capsule update will fail. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add imx91_11x11_evk_inline_ecc_defconfig to enable DDR inine ECC. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Because u-boot does not support SPI NAND device as env storage device. For flexspi NAND boot, load/store its env variables from MMC. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Updating the LVDS and Combo PHY settings to match the vendor datasheets and reference manual. For both PHYs (iMX8QM and iMX8QXP), the common mode voltage should be 6. For the LVDS only PHY (iMX8QM), the 'TST' field should be set to the default value of 0x25. Also, for the LVDS only PHY, the 'M' field should be set to 1 for the range form 44 MHz to 89 MHz. For the Combo PHY (iMX8QXP), the 'CO' field need to be set to 1 to select a PLL output divide of 2. Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
… characterization data Merge in LFAC/uboot-nxp from ~NXF60555/uboot-nxp-gaurav:lf_v2024.04 to lf_v2024.04 * commit '80b9c68e772a62f44a2226558b948f61a6c454ed': LFU-666: crypto/rng: imx8ulp: Confgure rng silicon characterization data
error observed ‘RTFRQMIN’ undeclared (first use in this function) sec_out32(&rng->rtfreqmin, RTFRQMIN); fixed the error by intorducing compile time macros. Fixes: 80b9c68 (LFU-666: crypto/rng: imx8ulp: Confgure rng silicon characterization data) Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
… IC bug workaround The i.MX95(A) Soc has an TXFOFO IC bug on USB controller, this will add a compatible "fsl,imx95a-dwc3" to filter it out, so the workaround can be applied to this Soc. Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
…XFIFO IC issue On i.MX95(A) Soc, USB3 TXFIFO(RAM1) memory range 0x84800-0x88000 is inaccessible, if write data to this memory the content is unchanged. When the host controller fetch data from this memory range and transmit the data to USB bus, data transfer error will occur. This issue happens when the controller use default configuration of TXFIFO (automatically calculated by HW). However, we can change the TXFIFO configuration by GTXFIFOSIZE* to workaround this issue. The host controller mainly uses TXFIFO for FS/LS, HS, SS and debug capability cases. The size and offset is controlled by GTXFIFOSIZE0, GTXFIFOSIZE1, GTXFIFOSIZE2 and GTXFIFOSIZE3 respectively. The default value of GTXFIFOSIZE0/1 does not span over issue memory. The default value of GTXFIFOSIZE2 is 0x02060811 and it means use memory 0x81030-0x850B8. With this change GTXFIFOSIZE2 will use memory 0x88000- 0x8C400. The default value of GTXFIFOSIZE3 is 0A170022 and it means use memory 0x850B8-0x851C8. With this change GTXFIFOSIZE3 will use memory 0x81030- 0x81140. This workaround is only for host mode. Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong value is used in ccm_reg structure and Coverity reports several issues as Out-of-bounds write. CID: 36648093, 36648094, 36648112, 36648113 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
In some ELE APIs, the msg variable doesn't write msg.data[0] when sending
message, but will read msg.data[0] value as ELE returns. However, there is
possibility that MU driver returns error, so the data[0] is not set by ELE
and not initialized either.
Coverity reports several Uninitialized scalar variable issues
CID: 36648095, 36648096, 36648107, 36648109, 36648111, 36648115,
36648120, 36648122
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
ROM use UID[0] and UID[1] as serial number with big endian when usb serial download. After update this, uuu(>1.6) can use below command to filter out devices when multi boards connected. uuu -ms <serial#> ... [sudo] uuu -lsusb can list known devices with serial# informaiton. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
After update this, uuu(>1.6) can use below command to filter out devices when multi boards connected. uuu -ms <serial#> ... [sudo] uuu -lsusb can list known devices with serial# informaiton. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
ROM use UID[0] and UID[1] as serial number with big endian when usb serial download. After update this, uuu(>1.6) can use below command to filter out devices when multi boards connected. uuu -ms <serial#> ... [sudo] uuu -lsusb can list known devices with serial# informaiton. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
To set the i.MX95 flexspi nor run in the optimal performance status, the by default flexspi FCB boot header was set to octal ddr 200Mhz mode. In SPL/U-boot, the CONFIG_SPI_FLASH_SOFT_RESET and CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT need to be enabled. To support the octal ddr mode, using the spi-nor-core driver instead of the spi-nor-tiny driver, SFDP support also need to be included to get all necessary parameters from the NOR chip discoverable table. Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by Ye Li <ye.li@nxp.com>
When checking the driver supports_op, the default_supports_op and the dtr_supports_op need to be distinguished. To support the high speed octal mode, the correct rx sample clk source and dll sample delay need to be set, porting these code back from Linux kernel. Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by Ye Li <ye.li@nxp.com>
To support the octal ddr mode for mt35xu01gaba, add all necessary info to ID table, but not all NOR chips has the SCCR register map table in SFDP, mt35xu01gaba is one of these, it only has the following tables: 4-byte Address Instruction Table - FF84 eXtended Serial Peripheral Interface (xSPI) Profile 1.0 - FF05 Command Sequences to change to Octal DDR (8D-8D-8D) mode - FF0A The current implementation still filter it out since no SCCR table found, but the Command Sequences to change to Octal DDR table also indiates the chip can use octal ddr mode. Add this workaround to enable octal ddr for this chip. Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by Ye Li <ye.li@nxp.com>
Change the flexspi clock rate to 200Mhz. Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by Ye Li <ye.li@nxp.com>
Commit f957e03 (LFU-671-2: spi: nxp_fspi: fix the issues for octal dtr mode) introduces build break on some Layerscape platforms which do not have DM clk driver enabled. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Add basic i.MX8MP NAVQ+ board support. Signed-off-by: Dmitry Bazhenov <dimab@voxelbotics.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Both typec supports Power delivery. Signed-off-by: Ye Li <ye.li@nxp.com>
When calling ELE API, res parameter will pass to ELE API to get ELE response value for failure. So most of usage does not initialize this variable and print it after calling ELE API. However, when ELE API returns failure, we can't ensure this res is always set because there may be other failure like MU failure. Fix it for coverity report CID 17916326 and 17916131 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Uninitialized res variable is used when calling ELE API and printed at failure. Need to initialize it to fix coverity report CID: 17916124, 36648101, 36648104 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Add "qb" check/save/erase commands. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
The iMX91 MAC address fuse order follows iMX93 Rev A1, however current check does not check soc id but only the revision. So wrong MAC address order is got from fuse. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
…lated configs Enable the flexspi octal ddr mode not only in the fspi config but in all i.MX95 19x19 EVK configs. Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
Enable lpi2c3 in u-boot pre-relocation phase, so we can use this bus for probing different i2c devices between EVK and audio board. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
The bus_format variable is not initialized, in case the fmt property is not set, it will cause problem to following codes. Fix coverity issue 37938122. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Increase FIT image buffer size to avoid inflate(-1) error when trying to boot from mmc.
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