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class Apicula(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Ascentlint(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Design_compiler(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam", "generic"] | ||
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@classmethod | ||
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class Gatemate(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Genus(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam", "generic"] | ||
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@classmethod | ||
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class Ghdl(Edatool): | ||
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argtypes = ["vlogparam", "generic"] | ||
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@classmethod | ||
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class Icestorm(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Mistral(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Modelsim(Edatool): | ||
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argtypes = ["plusarg", "vlogdefine", "vlogparam", "generic"] | ||
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@classmethod | ||
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class Openfpga(Edatool): | ||
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argtypes = ["plusarg", "vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Openlane(Edatool): | ||
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argtypes = ["vlogdefine"] | ||
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@classmethod | ||
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class Openroad(Edatool): | ||
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_description = """OpenROAD-flow-scripts | ||
""" | ||
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class Oxide(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Rivierapro(Edatool): | ||
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argtypes = ["plusarg", "vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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class Icepack(Edatool): | ||
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description = "Generate binary image for iCE40 FPGAs" | ||
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TOOL_OPTIONS = { | ||
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class Icetime(Edatool): | ||
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description = "Static timing analysis for iCE40 FPGAs" | ||
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TOOL_OPTIONS = { | ||
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class Nextpnr(Edatool): | ||
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description = "A portable FPGA place and route tool" | ||
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TOOL_OPTIONS = { | ||
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class Sv2v(Edatool): | ||
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description = "SystemVerilog to Verilog conversion" | ||
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TOOL_OPTIONS = { | ||
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class Trellis(Edatool): | ||
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argtypes = ["vlogdefine", "vlogparam"] | ||
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@classmethod | ||
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