Skip to content

feat: computable Q semantics wrt SMT-LIB spec #40

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
bollu merged 16 commits into from
Jan 30, 2026
Merged

feat: computable Q semantics wrt SMT-LIB spec #40

bollu merged 16 commits into from
Jan 30, 2026

Conversation

@bollu
Copy link
Contributor

@bollu bollu commented Jan 28, 2026

We add a computable version of the noncomputable SMT-LIB semantics,
by creating computable definitions for 'lower' and 'upper' adjoints of the
embedding of PackedFloat into ExtRat.

This should match the results of our RNE circuit, and mismatches will
help us identify bugs in either the SMT-LIB semantics or our RNE circuit.

@bollu
Copy link
Contributor Author

bollu commented Jan 29, 2026 •
edited
Loading 

===
🧪 ROUNDING MODE RNA

  ❌(RNA (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x00#5, sig := 0x00#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RNA (Q: ExtRat.Number (1 : Rat)/256); { state := num, num := { sign := false, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RNA): 896 successes, 2 failures, 99.777283% success rate
===
🧪 ROUNDING MODE RNE

  ❌(RNE (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x00#5, sig := 0x00#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RNE (Q: ExtRat.Number (1 : Rat)/256); { state := num, num := { sign := false, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RNE (Q: ExtRat.Number (1 : Rat)/128); { state := num, num := { sign := false, ex := 0x19#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RNE): 895 successes, 3 failures, 99.665924% success rate
===
🧪 ROUNDING MODE RTN

  ❌(RTN (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x00#5, sig := 0x00#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTN (Q: ExtRat.Number (1 : Rat)/256); { state := num, num := { sign := false, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTN (Q: ExtRat.Number (1 : Rat)/128); { state := num, num := { sign := false, ex := 0x19#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTN (Q: ExtRat.Number (3 : Rat)/256); { state := num, num := { sign := false, ex := 0x19#5, sig := 0x60#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTN (Q: ExtRat.Number (-1 : Rat)/256); { state := num, num := { sign := true, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number (-1 : Rat)/64); { state := num, num := { sign := true, ex := 0xa#4, sig := 0x10#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RTN): 893 successes, 5 failures, 99.443207% success rate
===
🧪 ROUNDING MODE RTP

  ❌(RTP (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x00#5, sig := 0x00#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTP (Q: ExtRat.Number (1 : Rat)/256); { state := num, num := { sign := false, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number (1 : Rat)/64); { state := num, num := { sign := false, ex := 0xa#4, sig := 0x10#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RTP): 896 successes, 2 failures, 99.777283% success rate
===
🧪 ROUNDING MODE RTZ

  ❌(RTZ (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x00#5, sig := 0x00#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTZ (Q: ExtRat.Number (1 : Rat)/256); { state := num, num := { sign := false, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTZ (Q: ExtRat.Number (1 : Rat)/128); { state := num, num := { sign := false, ex := 0x19#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }

  ❌(RTZ (Q: ExtRat.Number (3 : Rat)/256); { state := num, num := { sign := false, ex := 0x19#5, sig := 0x60#7 } }
    - SMT-LIB  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RTZ): 894 successes, 4 failures, 99.554566% success rate

We seem to have failures around various edge cases to do with zero, debugging to see if my SMT spec is wrong, or our rounding mode is wrong :)

@bollu bollu closed this Jan 29, 2026
@bollu bollu reopened this Jan 29, 2026
bollu added 5 commits January 29, 2026 16:41
@bollu
chore: fix
b47e63c
@bollu
chore: fix
f8952ed
@bollu
chore: fix zeroes
32bdb74 
===
🧪 ROUNDING MODE RNA
  📜 Final(RNA): 898 successes, 0 failures, 100.000000% success rate
===
🧪 ROUNDING MODE RNE
  📜 Final(RNE): 898 successes, 0 failures, 100.000000% success rate
===
🧪 ROUNDING MODE RTN

  ❌(RTN (Q: ExtRat.Number (-1 : Rat)/256); { state := num, num := { sign := true, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number (-1 : Rat)/64); { state := num, num := { sign := true, ex := 0xa#4, sig := 0x10#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := true, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RTN): 897 successes, 1 failures, 99.888641% success rate
===
🧪 ROUNDING MODE RTP

  ❌(RTP (Q: ExtRat.Number (1 : Rat)/256); { state := num, num := { sign := false, ex := 0x18#5, sig := 0x40#7 } }
    - SMT-LIB  (Q: ExtRat.Number (1 : Rat)/64); { state := num, num := { sign := false, ex := 0xa#4, sig := 0x10#5 } }
    - Circuit  (Q: ExtRat.Number 0); { state := num, num := { sign := false, ex := 0x0#4, sig := 0x00#5 } }
  📜 Final(RTP): 897 successes, 1 failures, 99.888641% success rate
===
🧪 ROUNDING MODE RTZ
  📜 Final(RTZ): 898 successes, 0 failures, 100.000000% success rate
@bollu
chore: try and correct semantics
1c89b23
@bollu
chore: merge
2235458
@bollu bollu mentioned this pull request Jan 30, 2026
Closed
@bollu bollu marked this pull request as ready for review January 30, 2026 11:48
@bollu bollu merged commit 6a2e3e2 into main Jan 30, 2026
2 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

1 participant

@bollu