[ConstraintElimination] Convert to unsigned Pred if possible.

Convert SLE/SLT predicates to unsigned equivalents if both operands are
known to be signed-positive.

https://alive2.llvm.org/ce/z/tBeiZr

llvm/lib/Transforms/Scalar/ConstraintElimination.cpp

@@ -19,6 +19,7 @@
 #include "llvm/Analysis/ConstraintSystem.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/IRBuilder.h"
@@ -110,7 +111,11 @@ class ConstraintInfo {
   ConstraintSystem UnsignedCS;
   ConstraintSystem SignedCS;
 
+  const DataLayout &DL;
+
 public:
+  ConstraintInfo(const DataLayout &DL) : DL(DL) {}
+
   DenseMap<Value *, unsigned> &getValue2Index(bool Signed) {
     return Signed ? SignedValue2Index : UnsignedValue2Index;
   }
@@ -326,6 +331,14 @@ ConstraintInfo::getConstraint(CmpInst::Predicate Pred, Value *Op0, Value *Op1,
       Pred != CmpInst::ICMP_SLE && Pred != CmpInst::ICMP_SLT)
     return {};
 
+  // If both operands are known to be non-negative, change signed predicates to
+  // unsigned ones. This increases the reasoning effectiveness in combination
+  // with the signed <-> unsigned transfer logic.
+  if (CmpInst::isSigned(Pred) &&
+      isKnownNonNegative(Op0, DL, /*Depth=*/MaxAnalysisRecursionDepth - 1) &&
+      isKnownNonNegative(Op1, DL, /*Depth=*/MaxAnalysisRecursionDepth - 1))
+    Pred = CmpInst::getUnsignedPredicate(Pred);
+
   SmallVector<PreconditionTy, 4> Preconditions;
   bool IsSigned = CmpInst::isSigned(Pred);
   auto &Value2Index = getValue2Index(IsSigned);
@@ -646,8 +659,6 @@ void ConstraintInfo::addFact(CmpInst::Predicate Pred, Value *A, Value *B,
              A->printAsOperand(dbgs(), false); dbgs() << ", ";
              B->printAsOperand(dbgs(), false); dbgs() << "'\n");
   bool Added = false;
-  assert(CmpInst::isSigned(Pred) == R.IsSigned &&
-         "condition and constraint signs must match");
   auto &CSToUse = getCS(R.IsSigned);
   if (R.Coefficients.empty())
     return;
@@ -743,7 +754,7 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT) {
   bool Changed = false;
   DT.updateDFSNumbers();
 
-  ConstraintInfo Info;
+  ConstraintInfo Info(F.getParent()->getDataLayout());
   State S(DT);
 
   // First, collect conditions implied by branches and blocks with their

llvm/test/Transforms/ConstraintElimination/signed-query-unsigned-system.ll

@@ -9,7 +9,7 @@ define i1 @sge_0_unsigned_a_ne_0(i8 %a) {
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[A_NE_0]])
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A]] to i16
 ; CHECK-NEXT:    [[T:%.*]] = icmp sge i16 [[EXT]], 0
-; CHECK-NEXT:    ret i1 [[T]]
+; CHECK-NEXT:    ret i1 true
 ;
   %a.ne.0 = icmp ne i8 %a, 0
   call void @llvm.assume(i1 %a.ne.0)
@@ -24,7 +24,7 @@ define i1 @sgt_0_unsigned_a_ne_0(i8 %a) {
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[A_NE_0]])
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A]] to i16
 ; CHECK-NEXT:    [[T:%.*]] = icmp sgt i16 [[EXT]], 0
-; CHECK-NEXT:    ret i1 [[T]]
+; CHECK-NEXT:    ret i1 true
 ;
   %a.ne.0 = icmp ne i8 %a, 0
   call void @llvm.assume(i1 %a.ne.0)
@@ -54,7 +54,7 @@ define i1 @sge_0_unsigned_a_sge_0(i8 %a) {
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[A_SGE_0]])
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A]] to i16
 ; CHECK-NEXT:    [[T:%.*]] = icmp sge i16 [[EXT]], 0
-; CHECK-NEXT:    ret i1 [[T]]
+; CHECK-NEXT:    ret i1 true
 ;
   %a.sge.0 = icmp sge i8 %a, 0
   call void @llvm.assume(i1 %a.sge.0)
@@ -69,7 +69,7 @@ define i1 @sgt_0_unsigned_a_ugt_0(i8 %a) {
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[A_UGT_0]])
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A]] to i16
 ; CHECK-NEXT:    [[T:%.*]] = icmp sgt i16 [[EXT]], 0
-; CHECK-NEXT:    ret i1 [[T]]
+; CHECK-NEXT:    ret i1 true
 ;
   %a.ugt.0 = icmp ugt i8 %a, 0
   call void @llvm.assume(i1 %a.ugt.0)
@@ -99,7 +99,7 @@ define i1 @sgt_1_unsigned_a_ugt_1(i8 %a) {
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[A_UGT_1]])
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A]] to i16
 ; CHECK-NEXT:    [[T:%.*]] = icmp sgt i16 [[EXT]], 1
-; CHECK-NEXT:    ret i1 [[T]]
+; CHECK-NEXT:    ret i1 true
 ;
   %a.ugt.1 = icmp ugt i8 %a, 1
   call void @llvm.assume(i1 %a.ugt.1)
@@ -133,8 +133,8 @@ define i1 @sgt_0_unsigned_a_ugt_neg_10(i8 %a) {
 ; CHECK-NEXT:    [[A_UGT_0:%.*]] = icmp ugt i8 [[A:%.*]], 10
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[A_UGT_0]])
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i8 [[A]] to i16
-; CHECK-NEXT:    [[T:%.*]] = icmp sgt i16 [[EXT]], 0
-; CHECK-NEXT:    ret i1 [[T]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i16 [[EXT]], 0
+; CHECK-NEXT:    ret i1 true
 ;
   %a.ugt.0 = icmp ugt i8 %a, 10
   call void @llvm.assume(i1 %a.ugt.0)