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[RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32Zdinx…
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…LD. (llvm#85877)

This allows the asm printer to print the stack spill/reload messages.
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@topperc
topperc authored Mar 27, 2024
1 parent 082e7c4 commit 4d03a9e
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Showing 2 changed files with 44 additions and 23 deletions.
35 changes: 28 additions & 7 deletions llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -312,10 +312,19 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
Register Hi =
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);

assert(MBBI->hasOneMemOperand() && "Expected mem operand");
MachineMemOperand *OldMMO = MBBI->memoperands().front();
MachineFunction *MF = MBB.getParent();
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);

BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
.add(MBBI->getOperand(2))
.setMemRefs(MMOLo);

if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
// FIXME: Zdinx RV32 can not work on unaligned memory.
assert(!STI->hasFastUnalignedAccess());
Expand All @@ -325,13 +334,15 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
.add(MBBI->getOperand(1))
.add(MBBI->getOperand(2));
.add(MBBI->getOperand(2))
.setMemRefs(MMOHi);
} else {
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
.add(MBBI->getOperand(1))
.addImm(MBBI->getOperand(2).getImm() + 4);
.addImm(MBBI->getOperand(2).getImm() + 4)
.setMemRefs(MMOHi);
}
MBBI->eraseFromParent();
return true;
Expand All @@ -349,14 +360,21 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
Register Hi =
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);

assert(MBBI->hasOneMemOperand() && "Expected mem operand");
MachineMemOperand *OldMMO = MBBI->memoperands().front();
MachineFunction *MF = MBB.getParent();
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);

// If the register of operand 1 is equal to the Lo register, then swap the
// order of loading the Lo and Hi statements.
bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
// Order: Lo, Hi
if (!IsOp1EqualToLo) {
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
.add(MBBI->getOperand(2))
.setMemRefs(MMOLo);
}

if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
Expand All @@ -365,20 +383,23 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
MBBI->getOperand(2).setOffset(Offset + 4);
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
.add(MBBI->getOperand(2))
.setMemRefs(MMOHi);
MBBI->getOperand(2).setOffset(Offset);
} else {
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
.addReg(MBBI->getOperand(1).getReg())
.addImm(MBBI->getOperand(2).getImm() + 4);
.addImm(MBBI->getOperand(2).getImm() + 4)
.setMemRefs(MMOHi);
}

// Order: Hi, Lo
if (IsOp1EqualToLo) {
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
.add(MBBI->getOperand(2))
.setMemRefs(MMOLo);
}

MBBI->eraseFromParent();
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32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -14,28 +14,28 @@
; CHECK-NEXT: .cfi_def_cfa_offset 2064
; CHECK-NEXT: lui t0, 1
; CHECK-NEXT: add t0, sp, t0
; CHECK-NEXT: sw a0, -2040(t0)
; CHECK-NEXT: sw a1, -2036(t0)
; CHECK-NEXT: sw a0, -2040(t0) # 4-byte Folded Spill
; CHECK-NEXT: sw a1, -2036(t0) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: sw a2, -2048(a0)
; CHECK-NEXT: sw a3, -2044(a0)
; CHECK-NEXT: sw a4, 2040(sp)
; CHECK-NEXT: sw a5, 2044(sp)
; CHECK-NEXT: sw a6, 2032(sp)
; CHECK-NEXT: sw a7, 2036(sp)
; CHECK-NEXT: sw a2, -2048(a0) # 4-byte Folded Spill
; CHECK-NEXT: sw a3, -2044(a0) # 4-byte Folded Spill
; CHECK-NEXT: sw a4, 2040(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw a5, 2044(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw a6, 2032(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw a7, 2036(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: lw a1, -2036(a0)
; CHECK-NEXT: lw a0, -2040(a0)
; CHECK-NEXT: lw a1, -2036(a0) # 4-byte Folded Reload
; CHECK-NEXT: lw a0, -2040(a0) # 4-byte Folded Reload
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: lw a2, -2048(a0)
; CHECK-NEXT: lw a3, -2044(a0)
; CHECK-NEXT: lw a4, 2040(sp)
; CHECK-NEXT: lw a5, 2044(sp)
; CHECK-NEXT: lw a6, 2032(sp)
; CHECK-NEXT: lw a7, 2036(sp)
; CHECK-NEXT: lw a2, -2048(a0) # 4-byte Folded Reload
; CHECK-NEXT: lw a3, -2044(a0) # 4-byte Folded Reload
; CHECK-NEXT: lw a4, 2040(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw a5, 2044(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw a6, 2032(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw a7, 2036(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
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