Latest (v0.0-3373-g54e37ed0) verison of Verible #542
MikeOpenHWGrouplint.yml
on: pull_request
Format Verilog Sources
25s
Vendor Up-to-Date
41s
Annotations
3 errors
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Format Verilog Sources:
rtl/core-v-mcu/components/apb_soc_ctrl.sv#L1
Files differ (M)
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Format Verilog Sources
Found differences, run util/format-verible before committing.
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Format Verilog Sources
Process completed with exit code 1.
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