-
Notifications
You must be signed in to change notification settings - Fork 52
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
[XIF] Interrupts cleared too late #507
Comments
This issue is similar to #325. A fix can maybe be done by blanking interrupts the cycle after receiving a load/store rvalid. The non-blanked interrupt presence should still lead to stop issuing new instructions in ID (otherwise blanking can be continued for a long series of loads/stores) |
Both CLIC and Basic should be studied and ideally same fix should be applied for both if needed |
Blanking interrupts for one cycle after a load or store has left WB. Refactored some assertions for CLIC, added a separate file for CLIC asserts. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
This issue should have been fixed with PR #655. The XIF was not taken into account, so this issue needs to be revisited once the XIF is properly implemented. The existing assertions will likely fail when X_EXT is set to 1. |
Renamed with XIF prefix |
If an interrupt is cleared via a (non-bufferable) store, then the interrupt on irq_i will go low in the cycle after the store instruction left the WB stage. As the irq_i lines are registered inside the core, a following instruction can still get to see the interrupt that was supposed to be cleared.
The text was updated successfully, but these errors were encountered: