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Updated cycle counts in the pipeline chapter. #942

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merged 3 commits into from
Sep 11, 2023
Merged

Updated cycle counts in the pipeline chapter. #942

merged 3 commits into from
Sep 11, 2023

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silabs-oysteink
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Updated cycle counts in the pipeline chapter.
ef8a3e8 
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
@silabs-oysteink silabs-oysteink added the Component:Doc For issues in the Documentation (e.g. for User Manual, README.md files) label Sep 8, 2023
Silabs-ArjanB
Silabs-ArjanB requested changes Sep 11, 2023
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docs/user_manual/source/pipeline.rst Outdated
@@ -87,11 +83,25 @@ and zero stall on the data-side memory interface.
| | 4 (target is a non-word-aligned | EX stage and will cause a flush of the IF stage (including |
| | non-RVC instruction) | prefetch buffer) and ID stage. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Instruction Fence | 5 | The FENCE.I instruction as defined in 'Zifencei' of the |
| Instruction Fence | 5 | The FENCE[.I] instructions are defined in 'Zifencei' of the |
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I assume that FENCE[.I] in the right most column is supposed to cover both fence and fence.i. If so, just add a separate row for the fence instruction as it is not part of Zifencei as implied now.

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Fixed

docs/user_manual/source/pipeline.rst Outdated
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zba, Zbb, Zbc, Zbs | 1 | All instructions from Zba, Zbb, Zbc, Zbs take 1 cycle. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zcmt | 2 | Tablejumps take 2 cycles. |
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Tablejumps -> Table jumps

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Fixed

docs/user_manual/source/pipeline.rst Outdated
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zcmt | 2 | Tablejumps take 2 cycles. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zcmp | 2 - 18 | The number of cycles depend on the number of registers |
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depend -> depends

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Fixed

docs/user_manual/source/pipeline.rst Outdated
| Zcmp | 2 - 18 | The number of cycles depend on the number of registers |
| | | saved or restored by the instructions. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zca, Zcb | 1 | Instructions from Zca and Zcv take 1 cycle. |
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Zcv -> Zcb

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Fixed

docs/user_manual/source/pipeline.rst Outdated
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Zca, Zcb | 1 | Instructions from Zca and Zcv take 1 cycle. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| WFI, WFE | 1 - | Instructions causing sleep will not retire until wakeup. |
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Is it really 1 - or is it for example 2 - ? Under what scenario can '1' happen?

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It should indeed be 2 -, unless we also specify behavior under debug mode which would simply be '1'. Not including debug mode for now.

docs/user_manual/source/pipeline.rst Outdated
@@ -100,7 +110,16 @@ The |corev| experiences a 1 cycle penalty on the following hazards.

* Load data hazard (in case the instruction immediately following a load uses the result of that load)
* Jump register (jalr) data hazard (in case that a jalr depends on the result of an immediately preceding non-load instruction)
* Any implicit CSR read in ID (mret or table jump) while any implicit or explicit CSR access is in the WB stage
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Any implicit CSR read -> An instruction causing an implicit CSR read
any implicit or explicit CSR access -> a CSR access instruction or an instruction causing an implicit CSR access

Same type of conversion for following lines

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Updated

docs/user_manual/source/pipeline.rst Outdated
@@ -100,7 +110,16 @@ The |corev| experiences a 1 cycle penalty on the following hazards.

* Load data hazard (in case the instruction immediately following a load uses the result of that load)
* Jump register (jalr) data hazard (in case that a jalr depends on the result of an immediately preceding non-load instruction)
* Any implicit CSR read in ID (mret or table jump) while any implicit or explicit CSR access is in the WB stage
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I know we don't do it consistently, but try to highlight instruction like jalr by quoting them as jalr now that you are editing this file anyway

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Fixed

docs/user_manual/source/pipeline.rst Outdated
* Any implicit CSR read in ID (mret or table jump) while any implicit or explicit CSR access is in the EX stage

.. note::
Implicit CSR reads are reads performed by non-CSR instructions or CSR instructions reading multiple CSR values.
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multiple CSR values -> reading CSR values from another CSR

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Fixed

@silabs-oysteink
Updates after review.
eb0070a 
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
@Silabs-ArjanB Silabs-ArjanB merged commit dc275be into openhwgroup:master Sep 11, 2023
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