zcmt changes

core/branch_unit.sv

@@ -31,6 +31,8 @@ module branch_unit #(
     input fu_data_t fu_data_i,
     // Instruction PC - ISSUE_STAGE
     input logic [CVA6Cfg.VLEN-1:0] pc_i,
+    // is zcmt instruction
+    input logic is_zcmt_i,
     // Instruction is compressed - ISSUE_STAGE
     input logic is_compressed_instr_i,
     // Branch unit instruction is valid - ISSUE_STAGE
@@ -46,18 +48,10 @@ module branch_unit #(
     // Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE
     output logic resolve_branch_o,
     // Branch exception out - TO_BE_COMPLETED
-    output exception_t branch_exception_o,
-    //zcmt
-    input logic is_zcmt_i
+    output exception_t branch_exception_o
 );
   logic [CVA6Cfg.VLEN-1:0] target_address;
   logic [CVA6Cfg.VLEN-1:0] next_pc;
-  logic is_zcmt_q;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (~rst_ni) is_zcmt_q <= '0;
-    else is_zcmt_q <= is_zcmt_i;
-  end
 
   // here we handle the various possibilities of mis-predicts
   always_comb begin : mispredict_handler
@@ -83,20 +77,18 @@ module branch_unit #(
     // we need to put the branch target address into rd, this is the result of this unit
     branch_result_o = next_pc;
     resolved_branch_o.pc = pc_i;
-    // There are only two sources of mispredicts:
+    // There are only three sources of mispredicts:
     // 1. Branches
     // 2. Jumps to register addresses
+    // 3. Zcmt instructions
     if (branch_valid_i) begin
-      if (is_zcmt_q) begin
+      // write target address which goes to PC Gen or select target address if zcmt
+      resolved_branch_o.target_address = (branch_comp_res_i) | is_zcmt_i ? target_address : next_pc;
+      resolved_branch_o.is_taken = is_zcmt_i ? 1'b1 : branch_comp_res_i;
+      if (is_zcmt_i) begin
         // Unconditional jump handling
-        resolved_branch_o.is_taken = 1'b1;
         resolved_branch_o.is_mispredict = 1'b1;  // miss prediction for ZCMT 
-        resolved_branch_o.target_address = target_address;  // Use calculated address directly
         resolved_branch_o.cf_type = ariane_pkg::Jump;
-      end else begin
-        // write target address which goes to PC Gen
-        resolved_branch_o.target_address = (branch_comp_res_i) ? target_address : next_pc;
-        resolved_branch_o.is_taken = branch_comp_res_i;
       end
       // check the outcome of the branch speculation
       if (ariane_pkg::op_is_branch(fu_data_i.operation)) begin

core/cache_subsystem/wt_dcache.sv

@@ -188,10 +188,10 @@ module wt_dcache
   // read controllers (LD unit and PTW/MMU)
   ///////////////////////////////////////////////////////
 
-  // 0 is used by MMU, 1 by READ access requests
+  // 0 is used by MMU or implicit read by zcmt, 1 by READ access requests
   for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports
     // set these to high prio ports
-    if ((k == 0 && CVA6Cfg.MmuPresent) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin
+    if ((k == 0 && (CVA6Cfg.MmuPresent || CVA6Cfg.RVZCMT )) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin
       assign rd_prio[k] = 1'b1;
       wt_dcache_ctrl #(
           .CVA6Cfg(CVA6Cfg),

core/compressed_decoder.sv

@@ -876,7 +876,6 @@ module compressed_decoder #(
                 instr_o = instr_i;
               end else if (instr_i[12:10] == 3'b000) begin  //jt/jalt instruction
                 is_zcmt_instr_o = 1;
-                instr_o = instr_i;
               end else begin
                 illegal_instr_o = 1'b1;
               end

core/csr_regfile.sv

@@ -18,6 +18,7 @@ module csr_regfile
 #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg            = config_pkg::cva6_cfg_empty,
     parameter type                   exception_t        = logic,
+    parameter type                   jvt_t              = logic,
     parameter type                   irq_ctrl_t         = logic,
     parameter type                   scoreboard_entry_t = logic,
     parameter type                   rvfi_probes_csr_t  = logic,
@@ -169,8 +170,7 @@ module csr_regfile
     // RVFI
     output rvfi_probes_csr_t rvfi_csr_o,
     //jvt output
-    output logic [CVA6Cfg.XLEN-1:6] jvt_base_o,
-    output logic [5:0] jvt_mode_o
+    output jvt_t jvt_o
 );
 
   localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg);
@@ -355,7 +355,11 @@ module csr_regfile
           end
         end
         riscv::CSR_JVT: begin
-          csr_rdata = {jvt_q.base, jvt_q.mode};
+          if (CVA6Cfg.RVZCMT) begin
+            csr_rdata = {jvt_q.base, jvt_q.mode};
+          end else begin
+            read_access_exception = 1'b1;
+          end
         end
         // non-standard extension
         riscv::CSR_FTRAN: begin
@@ -1068,8 +1072,12 @@ module csr_regfile
         if (CVA6Cfg.DebugEn) dscratch1_d = csr_wdata;
         else update_access_exception = 1'b1;
         riscv::CSR_JVT: begin
-          jvt_d.base = csr_wdata[CVA6Cfg.XLEN-1:6];
-          jvt_d.mode = 6'b000000;
+          if (CVA6Cfg.RVZCMT) begin
+            jvt_d.base = csr_wdata[CVA6Cfg.XLEN-1:6];
+            jvt_d.mode = 6'b000000;
+          end else begin
+            update_access_exception = 1'b1;
+          end
         end
         // trigger module CSRs
         riscv::CSR_TSELECT: update_access_exception = 1'b1;  // not implemented
@@ -2464,8 +2472,8 @@ module csr_regfile
   assign frm_o = fcsr_q.frm;
   assign fprec_o = fcsr_q.fprec;
   //JVT outputs
-  assign jvt_base_o = jvt_q.base;
-  assign jvt_mode_o = jvt_q.mode;
+  assign jvt_o.base = jvt_q.base;
+  assign jvt_o.mode = jvt_q.mode;
   // MMU outputs
   assign satp_ppn_o = CVA6Cfg.RVS ? satp_q.ppn : '0;
   assign vsatp_ppn_o = CVA6Cfg.RVH ? vsatp_q.ppn : '0;
@@ -2738,7 +2746,7 @@ module csr_regfile
   // RVFI
   //-------------
   assign rvfi_csr_o.fcsr_q = CVA6Cfg.FpPresent ? fcsr_q : '0;
-  assign rvfi_csr_o.jvt_q = jvt_q;
+  assign rvfi_csr_o.jvt_q = CVA6Cfg.RVZCMT ? jvt_q : '0;
   assign rvfi_csr_o.dcsr_q = CVA6Cfg.DebugEn ? dcsr_q : '0;
   assign rvfi_csr_o.dpc_q = CVA6Cfg.DebugEn ? dpc_q : '0;
   assign rvfi_csr_o.dscratch0_q = CVA6Cfg.DebugEn ? dscratch0_q : '0;

core/cva6.sv

@@ -86,6 +86,11 @@ module cva6
       branchpredict_sbe_t     branch_predict; // this field contains branch prediction information regarding the forward branch path
       exception_t             ex;             // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions
     },
+    //JVT struct{base,mode}
+    localparam type jvt_t = struct packed {
+      logic [CVA6Cfg.XLEN-7:0] base;
+      logic [5:0] mode;
+    },
 
     // ID/EX/WB Stage
     localparam type scoreboard_entry_t = struct packed {
@@ -113,6 +118,7 @@ module cva6
       logic is_last_macro_instr;  // is last decoded 32bit instruction of macro definition
       logic is_double_rd_macro_instr;  // is double move decoded 32bit instruction of macro definition
       logic vfp;  // is this a vector floating-point instruction?
+      logic is_zcmt;  //is a zcmt instruction
     },
     localparam type writeback_t = struct packed {
       logic valid;  // wb data is valid
@@ -415,6 +421,7 @@ module cva6
 
   fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_id_ex;
   logic [CVA6Cfg.VLEN-1:0] pc_id_ex;
+  logic zcmt_id_ex;
   logic is_compressed_instr_id_ex;
   logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_ex;
   // fixed latency units
@@ -564,9 +571,7 @@ module cva6
   logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr;
   logic [31:0] mcountinhibit_csr_perf;
   //jvt
-  logic [CVA6Cfg.XLEN-1:6] jvt_base;
-  logic [5:0] jvt_mode;
-  logic is_zcmt_id_is, is_zcmt_is_ex;
+  jvt_t jvt;
   // ----------------------------
   // Performance Counters <-> *
   // ----------------------------
@@ -681,6 +686,7 @@ module cva6
       .dcache_req_o_t(dcache_req_o_t),
       .exception_t(exception_t),
       .fetch_entry_t(fetch_entry_t),
+      .jvt_t(jvt_t),
       .irq_ctrl_t(irq_ctrl_t),
       .scoreboard_entry_t(scoreboard_entry_t),
       .interrupts_t(interrupts_t),
@@ -725,9 +731,7 @@ module cva6
       .compressed_resp_i (x_compressed_resp),
       .compressed_valid_o(x_compressed_valid),
       .compressed_req_o  (x_compressed_req),
-      .jvt_base_i        (jvt_base),
-      .jvt_mode_i        (jvt_mode),
-      .is_zcmt_o         (is_zcmt_id_is),
+      .jvt_i             (jvt),
       // DCACHE interfaces
       .dcache_req_ports_i(dcache_req_ports_cache_id),
       .dcache_req_ports_o(dcache_req_ports_id_cache)
@@ -826,13 +830,12 @@ module cva6
       .decoded_instr_valid_i   (issue_entry_valid_id_issue),
       .is_ctrl_flow_i          (is_ctrl_fow_id_issue),
       .decoded_instr_ack_o     (issue_instr_issue_id),
-      .is_zcmt_i               (is_zcmt_id_is),
-      .is_zcmt_o               (is_zcmt_is_ex),
       // Functional Units
       .rs1_forwarding_o        (rs1_forwarding_id_ex),
       .rs2_forwarding_o        (rs2_forwarding_id_ex),
       .fu_data_o               (fu_data_id_ex),
       .pc_o                    (pc_id_ex),
+      .is_zcmt_o               (zcmt_id_ex),
       .is_compressed_instr_o   (is_compressed_instr_id_ex),
       .tinst_o                 (tinst_ex),
       // fixed latency unit ready
@@ -924,6 +927,7 @@ module cva6
       .rs2_forwarding_i(rs2_forwarding_id_ex),
       .fu_data_i(fu_data_id_ex),
       .pc_i(pc_id_ex),
+      .is_zcmt_i(zcmt_id_ex),
       .is_compressed_instr_i(is_compressed_instr_id_ex),
       .tinst_i(tinst_ex),
       // fixed latency units
@@ -1034,8 +1038,7 @@ module cva6
       .pmpaddr_i               (pmpaddr),
       //RVFI
       .rvfi_lsu_ctrl_o         (rvfi_lsu_ctrl),
-      .rvfi_mem_paddr_o        (rvfi_mem_paddr),
-      .is_zcmt_i               (is_zcmt_is_ex)
+      .rvfi_mem_paddr_o        (rvfi_mem_paddr)
   );
 
   // ---------
@@ -1095,6 +1098,7 @@ module cva6
   csr_regfile #(
       .CVA6Cfg           (CVA6Cfg),
       .exception_t       (exception_t),
+      .jvt_t             (jvt_t),
       .irq_ctrl_t        (irq_ctrl_t),
       .scoreboard_entry_t(scoreboard_entry_t),
       .rvfi_probes_csr_t (rvfi_probes_csr_t),
@@ -1171,8 +1175,7 @@ module cva6
       .pmpcfg_o                (pmpcfg),
       .pmpaddr_o               (pmpaddr),
       .mcountinhibit_o         (mcountinhibit_csr_perf),
-      .jvt_base_o              (jvt_base),
-      .jvt_mode_o              (jvt_mode),
+      .jvt_o                   (jvt),
       //RVFI
       .rvfi_csr_o              (rvfi_csr)
   );
@@ -1277,8 +1280,7 @@ module cva6
   dcache_req_o_t [NumPorts-1:0] dcache_req_from_cache;
 
   // D$ request
-  // D$ request
-  if (CVA6Cfg.RVZCMT) begin
+  if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin // Cache port 0 is ultilize in implicit read access in ZCMT extension. Therefore, MMU should be turn off.           
     assign dcache_req_to_cache[0] = dcache_req_ports_id_cache;
   end else begin
     assign dcache_req_to_cache[0] = dcache_req_ports_ex_cache[0];
@@ -1289,7 +1291,7 @@ module cva6
                                                                           dcache_req_ports_acc_cache[1];
 
   // D$ response
-  if (CVA6Cfg.RVZCMT) begin
+  if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin // Cache port 0 is ultilize in implicit read access in ZCMT extension. Therefore, MMU should be turn off.
     assign dcache_req_ports_cache_id = dcache_req_from_cache[0];
   end else begin
     assign dcache_req_ports_cache_ex[0] = dcache_req_from_cache[0];

core/cva6_rvfi.sv

@@ -344,7 +344,7 @@ module cva6_rvfi
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags)
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm)
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_q.frm `COMMA csr.fcsr_q.fflags})
-  `CONNECT_RVFI_FULL(1, jvt, { csr.jvt_q.base `COMMA csr.jvt_q.mode})
+  `CONNECT_RVFI_FULL(CVA6Cfg.RVZCMT, jvt, { csr.jvt_q.base `COMMA csr.jvt_q.mode})
 
   `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec)
   `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr)

core/decoder.sv

@@ -87,8 +87,7 @@ module decoder
     // Is a control flow instruction - ISSUE_STAGE
     output logic is_control_flow_instr_o,
     //zcmt instruction
-    input logic is_zcmt_i,
-    output logic is_zcmt_o
+    input logic is_zcmt_i
 );
   logic illegal_instr;
   logic illegal_instr_bm;
@@ -181,10 +180,10 @@ module decoder
     instruction_o.use_zimm                 = 1'b0;
     instruction_o.bp                       = branch_predict_i;
     instruction_o.vfp                      = 1'b0;
+    instruction_o.is_zcmt                  = is_zcmt_i;
     ecall                                  = 1'b0;
     ebreak                                 = 1'b0;
     check_fprm                             = 1'b0;
-    is_zcmt_o                              = 1'b0;
 
     if (~ex_i.valid) begin
       case (instr.rtype.opcode)
@@ -1408,7 +1407,6 @@ module decoder
           imm_select              = JIMM;
           instruction_o.rd        = instr.utype.rd;
           is_control_flow_instr_o = 1'b1;
-          is_zcmt_o               = is_zcmt_i;
         end
 
         riscv::OpcodeAuipc: begin

core/ex_stage.sv

@@ -47,6 +47,8 @@ module ex_stage
     input fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_i,
     // PC of the current instruction - ISSUE_STAGE
     input logic [CVA6Cfg.VLEN-1:0] pc_i,
+    // is_zcmt instruction
+    input logic is_zcmt_i,
     // Report whether instruction is compressed - ISSUE_STAGE
     input logic is_compressed_instr_i,
     // Report instruction encoding - ISSUE_STAGE
@@ -228,9 +230,7 @@ module ex_stage
     // Information dedicated to RVFI - RVFI
     output lsu_ctrl_t rvfi_lsu_ctrl_o,
     // Information dedicated to RVFI - RVFI
-    output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o,
-    //zcmt instruction
-    input logic is_zcmt_i
+    output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o
 );
 
   // -------------------------
@@ -322,15 +322,15 @@ module ex_stage
       .debug_mode_i,
       .fu_data_i         (one_cycle_data),
       .pc_i,
+      .is_zcmt_i,
       .is_compressed_instr_i,
       .branch_valid_i    (|branch_valid_i),
       .branch_comp_res_i (alu_branch_res),
       .branch_result_o   (branch_result),
       .branch_predict_i,
       .resolved_branch_o,
       .resolve_branch_o,
-      .branch_exception_o(flu_exception_o),
-      .is_zcmt_i         (is_zcmt_i)
+      .branch_exception_o(flu_exception_o)
   );
 
   // 3. CSR (sequential)