Software TG report to TWG. (#433)

Files changed:

	* program/TG-reports-for-TWG/2021/20210726-sw-tg.md: Created.

Signed-off-by: Jeremy Bennett <jeremy.bennett@embecosm.com>

program/TG-reports-for-TWG/2021/20210726-sw-tg.md

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+# Software TG Report July 2021
+
+Presented to TWG meeting 26 July 2021.
+
+## Actions from most recent meetings
+
+Actions from [minutes of 12 July 2021](https://github.com/openhwgroup/core-v-sw/blob/master/meetings/2021/2021-07-12-minutes.md)
+
+- **Richard Barry** to make a central list of all the different hardware FreeRTOS must support. Initially via Mattermost, but can be committed to the [core-v-sw](https://github.com/openhwgroup/core-v-sw) repository in the [projects/freertos](https://github.com/openhwgroup/core-v-sw/tree/master/projects/freertos) directory.
+
+- **Robert Balas** and **Shteryana Shopova** to consider running separate monthly calls for all those interested in FreeRTOS to coordinate actions.
+
+- **All** to consider leading the SDK project.
+
+## Reports on active projects
+
+Links to reports on four Software TG projects and one joint Software/Hardware TG project.
+
+* [IDE report](https://github.com/openhwgroup/core-v-sw/blob/master/projects/ide/2021/monthly-report-2021-07-12.md)
+
+  - At Project Concept stage.
+  - Next month:
+
+	- Focus on PlatformIO integration.
+	- Continue to ask for examples of applications to include
+	- Speaking at upcoming RISC-V forum
+
+* [GNU Tools report](https://github.com/openhwgroup/core-v-sw/blob/master/projects/gnu-tools/2021/monthly-report-2021-07-12.md):
+
+  - At Project Concept stage.
+  - This month
+	- Can now run regression tests on the PULP simulator, GVSoC
+	- Have run CORE-V specific tests
+
+  - Next month:
+
+	- Need to merge remaining instructions into binutils, waiting on a rebase
+	- Work on fixing simulator failures
+	- Work on GCC
+
+* [FreeRTOS report](https://github.com/openhwgroup/core-v-sw/blob/master/projects/freertos/2021/monthly-report-12-july-21.md):
+
+  - At Project Concept stage.
+  - This month:
+
+    - made a few changes to configuration and compile time options, so can also target CVA6.
+	- formulated a plan to contribute upstream.
+
+  - Next month:
+
+	- Richard Barry to make central list of different hardware configurations to be supported.
+    - consider mid-month meetings just for FreeRTOS
+
+  - No risk register changes.
+
+* [Clang/LLVM Tools report](https://github.com/openhwgroup/core-v-sw/blob/master/projects/clang-llvm/2021/monthly-report-2021-07-12.md):
+
+  - At Project Concept stage.
+  - CVA6
+
+    - This month
+
+	  - Scripted builds now supported alongside GCC. Supports versions with GNU ld and LLVM LLD.
+	  - Fix to assembly level support of signalling NaN floating point in RISC-V assembly.
+	  - Align CI/CD with CVA6 reorganization.
+
+		  - GCC and both LLVM variants both agree on test results for CVA6
+
+	- Next month
+
+	  - finalize transition to new reorg
+	  - fix any test issues
+	  - do benchmarking.
+
+  - CV32E40P
+
+    - No change this month
+
+  - No risk register changes.
+
+* [Hardware Abstraction Layer report](https://github.com/openhwgroup/core-v-sw/blob/master/projects/hal/2021/monthly-report-2021-07-12.md)
+
+  - At Project Concept phase
+  - This month: comparison of options for HAL now on Mattermost for comment
+  - Next month: Will start on minimal demo
+
+* [Verilator modeling report to Software TG](https://github.com/openhwgroup/core-v-docs/blob/master/hw/projects/verilator-model/2021/20210712-report.md) and [Verilator modeling report to Hardware TG](https://github.com/openhwgroup/core-v-docs/blob/master/hw/projects/verilator-model/2021/202100721-report.md).  Note that this is Hardware TG led project, so this is only a report on the software component.
+
+  - At Project Concept stage.
+  - This month:
+
+    - [project plan and risk register](https://docs.google.com/spreadsheets/d/1Sl_GIklam3redWNj_DRVRVVBD49LvLD8k1zeFsJXllc) updated;
+	- software can now read and write DMI registers;
+	- incorect behavior in CORE-V-MCU debug unit raised as issue [#150](https://github.com/openhwgroup/core-v-mcu/issues/150);
+	- 6 milestones: milestone 1 complete, milestone 2 progress 42%; and
+	- 4-5 week delay due to lack of resource and unanticipate complexity in modeling the debug module.
+
+  - Next month:
+
+    - complete JTAG driver (DMI driver, DMI, DTM and TAP tests); and
+	- start work on initial Embdebug target library for CORE-V-MCU
+
+  - [Risk register](https://docs.google.com/spreadsheets/d/1Sl_GIklam3redWNj_DRVRVVBD49LvLD8k1zeFsJXllc) changes:
+
+    - likelihood increased for expert staff shortage;
+	- new risk that estimates of effort are too low - mitigation is addressing highest risk items first and choosing simplest designs throughout.
+
+## Upcoming projects
+
+* **Requirements for CORE-V MCU developer board SDK**
+
+  - Initial outline for Project Concept.
+  - Key action is to identify strong, experienced project lead for SDK.
+
+* **Linux integration**
+
+  - No update this month.
+
+* **Generalization of tools to other CORE-V architectures**
+
+  - No update this month.
+
+
+Jeremy Bennett, Chair\
+Yunhai Shang, Vice-Chair