Added August HW TG meeting notes

hw/MeetingMinutes/2021-04-21/2021-04-21_minutes.md

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+# HW TG Meeting: April 21, 2021
+
+## Attendees:
+- Hugh Pollitt-Smith
+- Duncan Bees
+- Arjan Bink
+- Davide Schiavone
+- Jeremy Bennett
+- Olive Zhao
+- Rick O’Connor
+- Tim Saxe
+- Vincent Cui
+- Yunhai Shang
+
+## Agenda:
+- Alibaba CSI HAL
+- CORE-V-MCU Project
+
+
+ ##Discussion notes:
+
+### Alibaba CSI HAL:
+  *  Vincent and Yunhai presented Alibaba’s THEAD CSI interface
+    * CSI is based on CMSIS, but further developed by Alibaba to fit their own requirements
+    * It appears the environment is big, complex—how well will this work on small chips like cv32e40p/x/s, or OSs like FreeRTOS; for CORE-V-MCU, we’re looking for abstraction of the lowest level of the hardware layer
+      * Current system supports Alibaba RTOS
+      * This should support multiple operating systems, including FreeRTOS, Zephyr; also other OSes, devices for CORE-V; we don’t want to lock developers into a particular RTOS; FreeRTOS is a current need for CORE-V-MCU
+    * Tim is interested to look at further, if there is a repo someone can point him to
+    * User Guide is currently in Mandarin only; Yunhai will share with Olive and Tim
+       * Olive can assess the level of effort to port CSI to the current CORE-V-MCU FPGA emulation
+    * Quicklogic have done their own HAL for CORE-V-MCU, but will switch to whatever SW TG comes up with
+      * Open question whether to push out emulation with current HAL or wait; don’t want to send people down the wrong path at the beginning
+    * There will not likely be a single HAL; CMSIS—lots of adoption already, but unlikely to be architecture agnostic; NMSIS — a few vendors getting together to advance it as an option; Alibaba with CSI
+      * For OpenHW, we should base decisions on community adoption, volume of support around different initiatives, consider what will help with adoption of the HW; is it for OpenHW Group to lead, follow, or wait for dust to settle and then implement? 
+      * Adopt a direction that is well-supported, driven by existence of adoption and volume; count architectures that have used the various implementations; put a matrix table together of options, position in industry, pros/cons for support by OpenHW
+           * Adoption is important, but also willingness to move to CORE-V; someone will need to pony up effort to move to CORE-V and provide support
+           * We want to follow the direction of RISC-V International
+    * Yunhai will lead this effort through the SW TG; first step will be a survey of available options (May); build consensus and way forward, leading to format proposal (June)
+
+
+
+### CORE-V-MCU SOC/FPGA project update:
+
+  * Duncan showed the current Project Plan spreadsheet; task breakdown is complete, but needs more details (start/complete dates) to get into shape for Monday’s TWG; Duncan, Tim, Hugh will meet to fill out checklist before Monday
+

hw/MeetingMinutes/2021-05-19/2021-05-19_minutes.md

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+# HW TG May 19 Meeting:
+
+## Attendees:
+- Hugh Pollitt-Smith
+- Anthony Le
+- Li Chen
+- Duncan Bees
+- Florain Zaruba
+- Greg Martin
+- Jeremy Bennett
+- Mike Thompson
+- Olive Zhao
+- Randy Oyadomari
+- Rick O’Connor
+- Tim Saxe
+
+
+## Agenda and discussion:
+
+
+## 1. CORE-V-MCU Verilator
+
+  * Jeremy has picked up the work from Florian, created a simple loop that puts the processor through reset and then runs the clock
+    * Performance is low (30kHz—the PULP model runs at 800kHz with some tuning)
+  * Concern about the number of warnings when running Verilator
+    * 944 warnings
+    * Need an action to deal with all the warnings; Jeremy will raise the issue in Github and we can triage from there
+  * Next step is to replace simple test bench with debug server (Embdebug); there appears to be a gap in the documentation regarding what the JTAG registers mean
+    * Florian suggested Jeremy open an issue to fix the documentation
+    * The JTAG registers are described in the RISC-V Debug Specification 0.13 (Section 6.1 Debug Transport Module)
+  * Randy from QuickLogic will bring up Verilator for CI; boot from a ROM and run tests
+  * Jeremy, Duncan, Randy, and Florian will update the project concept document; agreed to meet on Friday for further discussion
+
+
+## 2. CORE-V-MCU Verification IP
+
+  * We discussed Mike’s research and recommendations on Verification IP needs for CORE-V-MCU
+  * Overall, it’s a fairly bleak landscape on what is ready available
+  * There should be an effort to get fully-verified peripherals that anyone can use
+  * The block diagram on Slide 2 currently doesn’t exist; we emulate on FPGA, which is not satisfactory for CI purposes
+  * We can put some peripherals into a kind of loopback mode
+    * Hook UART1 TX to UART2 RX
+    * I2C master can talk to I2C slave
+    * Build a simple behavioural model for QSPI (write 4 bytes, read 4 bytes)
+    * For camera, use PWM output to generate sync signals, and use GPIO for data
+    * JTAG debug model is coming from Jeremy
+    * SDIO still needs a solution
  
+  * Does Renode fit into this picture? AntMicro may have some models for these peripherals
+    * Tim can ask if they have models
+    * We want to ensure models are written in Verilog so they can be used in a variety of simulators
+  * Start with simple models that get more interesting over time
+  * Action: create a test bench directory in core-v-mcu repo with subdirectories for each component (uart, etc.)
+    * One day, these may get migrated to separate repos and become a reference set; OpenHW Group can become the place for high quality open source VIP
+  * Mike will post updated version of his slides to reflect feedback

hw/MeetingMinutes/2021-06-16/2021-06-16_minutes.md

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+# HW TG - June 16, 2021
+
+## Attendees:
+- Hugh Pollitt-Smith
+- Anthony Le
+- Arjan Bink
+- Li Chen
+- Davide Schiavone
+- Duncan Bees
+- Florian Zaruba
+- Greg Martin
+- Zongru Li
+- Olive Zhao
+- Richard Barry
+- Rick O’Connor
+- Tim Saxe
+
+## Agenda:
+1. Introductory presentation by Dr. Li Chen, University of Saskatchewan
+  * Li’s research is in radiation tolerant/hardened ASICs, including microprocessors; has an interest to implement CV32E40P-based platform using rad-hard libraries
+  * Li was not sure about the complexity of core-v-mcu versus PULPissimo
+    * Core-v-mcu is designed to be parametrizable, and it should be straightforward to strip the platform down to a minimal set of elements (no eFPGA, minimal I/O)
+    * Greg (QuickLogic) can advise on how to do this; Tim can setup call with Li and his students and Greg to discuss
+2. Regression/CI discussion
+  * Richard (AWS) wants to setup a core-v-mcu board in their remote test lab along with several other RISC-V chips to run CI tests for FreeRTOS every evening
+  * Aim is to have one FreeRTOS kernel port across multiple RISC-V cores
+  * For core-v-mcu, the FPGA platform (Digilent NexsyA7-100T, Genesys2) is fine; noted that Genesys2 will eventually support the 64-bit core as well
+    * Need to be able to remote flash the device, observe output (e.g., UART) to see if tests pass or fail
+    * Hugh will send Richard info on the boards and components required for setup
+    * This is similar to what QuickLogic have setup already with NexysA7-100T board
+    * Eventually this would also support the core-v-mcu SOC development board
+  * Amazon has FPGAs in the cloud also—would they want to use those? Probably not for Richard’s CI/CD, but could be useful to expose to other people
+    * Cloud CI/CD is handled by another AWS person who is off this month; he would know about cloud-hosted FPGA
+  * Florian took an action to setup a discussion for technical issues
+3. Integrating CV32E40S with core-v-mcu
+  * CV32E40S core is in development, led by Silabs; 32-bit embedded class core with security features/extensions
+  * Project team is assessing if there is interest to have core integrated in core-v-mcu
+    * Intent is not to impact the current core-v-mcu tape-out with CV32E40P (Fall 2021)
+    * QuickLogic is working to have core-v-mcu parameterized to make the back-end flows easier to manage; would need to understand if this is a total rework, or if this can be handled via parameters/options
+    * Unibo team is working on a CV32E40S test chip, not under OpenHW Group
+    * Li Chen is interested in potentially implementing with his rad-hard library; this could be a good candidate project for the OpenHW Accelerate program
+4. Core-v-mcu project
+  * Anthony (QuickLogic) presented development board specs/options, and will post slides
+  * It is beneficial to make distinction between an eval board with  I/O isolation and test points, versus a development kit; OpenHW wants to build development kits in some volume (up to 10000) that is focussed on SW developers
+    * Characterization/eval board 10-20 boards, several 1000s per run; ~$1000 each
+  * Could be a 2-board solution
+    * Researchers in CMC’s community would probably be interested in doing power measurements, etc., versus pure software development
+    * CMC will manufacture and sell the boards
+    * Development kit should offer over air update

hw/MeetingMinutes/2021-07-21/2021-07-21_minutes.md

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+## HW TG - July 21, 2021
+
+### Attendees:
+- Hugh Pollitt-Smith
+- Anthony Le
+- Davide Schiavone
+- Duncan Bees
+- Greg Martin
+- Jeremy Bennett
+- Tim Saxe
+
+### Agenda/notes:
+
+- CORE-V-MCU SoC update
+    - Quicklogic targeting soft RTL freeze for end of July
+    - Greg will get in touch with Jeremy regarding number of harts in the platform, align the debug core with the MCU hardware
+    - Greg still has an open pull request under review; anticipate another one for end of July soft RTL freeze
+    - Tim will send Duncan a copy of the MCU checklist
+- CORE-V-MCU DevKit/SDK
+    - Duncan presented slides/diagrams showing relationships between the various CORE-V-MCU projects
+        - Duncan and Jeremy will revise and present at the TWG (July 26)
+    - The DevKit is the whole thing that you ship to the customer (hardware, SDK, tools, simulation, etc.); 
+        - SDK is delivered via the Quickstart Guide (i.e., instructions where/how to download and install)
+        - First version of the SDK will not include HAL and would be specific to the CORE-V-MCU; eventually SDK will be generic and will drive other architectures
+    - Verilator modeling project is specific to the CORE-V-MCU, but could be used for other cores
+    - For the SDK, don’t underestimate the level of effort required to develop; needs funding/resource commitments, testing, integration, documentation, training/videos
+        - Need a project lead who knows how to put a SDK together
+        - Will need commitments from the other SW projects in terms of delivering to a schedule
+        - SDK project concept could be created before a project leader is identified
+        - SDK should be pulling together things that already exist—is there a MVP version of each of the SW components?
+            - Identify specific versions/tags for each of the components
+    - Embedded FPGA flow (Symbiflow) is also part of the ecosystem, but not part of the SDK; it will need to be part of the Quickstart Guide as well
+    - Anthony will post slides in the HW DevKit Mattermost channel to get feedb

hw/MeetingMinutes/2021-08-18/2021-08-18_minutes.md

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+### HW TG - August 18, 2021:
+
+#### Agenda:
+* CORE-V-MCU Verilator update
+* CORE-V-MCU SoC update
+* Bootrom discussion/alignment
+* CORE-V-MCU Program discussion (see Duncan's note [here](https://mattermost.openhwgroup.org/all-users/channels/twg--hw/qxnab8og6bng8krj8znrw1ugze))
+* Fixing hardware issues found by software Teams (action from last week's SW TG)
+    * Raise issues; not access to the repo ; suggest/assign; at the stage where we know what to do; raise issue for the HW team.
+
+
+#### Attendees:
+- Hugh Pollitt-Smith
+- Anthony Le
+- Duncan Bees
+- Florian Zaruba
+- Greg Martin
+- Jeremy Bennett
+- Olive Zhao
+- Rick O’Connor
+- Tim Saxe
+
+
+#### Discussion notes:
+- Verilator modelling project update:
+    - Project is currently running 8 weeks behind and could be 16 weeks late by the end (see Jeremy’s report [here](https://github.com/openhwgroup/core-v-docs/blob/master/hw/projects/verilator-model/2021/20210819-hwtg-report.md))
+    - Discussion on the debug unit:
+        - Noted that there are issues with the debug unit; concern that there is a need to better verify the HW of the debug unit
+        - Who owns the debug unit? It is currently maintained by PULP, not OpenHW Group; there is a need to bring the debug module Ito OpenHW Group
+            - Implementation spans CORES and HW TGs; also need to consider where it sits in Verification
+            - Debug unit and the core (CV32E40P, CVA6, etc.) need to be verified in conjunction; every time we create a new CV core, we also need to verify that the debug unit and core are compatible
+        - In the short term, we require some RTL changes that need to be solved before we get to final silicon for core-v-mcu
+            - Florian can do this for the tape-out; Jeremy will provide reproducible snapshots/traces
+- CORE-V-MCU Update
+    - Greg presented slides (will post)
+    - How to manage PR against dev branch; Greg is in process of becoming a committer and will be able to merge his own PRs to keep dev branch up to date; will leave to Florian, Davide, Mike, to merge dev into master
+    - Something happened in the last few commits to the master branch to fix the number of harts issue
+    - Should CLI test be associated with core-v-mcu repo?
+        - There is already some SW within the core-v-mcu repo
+        - SW that is needed for the HW should build with the HW
+            - Current bootrom directory is a remnant of the PULP platform; replace current bootrom with the Greg’s new bootrom
+            - Verilator model uses the old bootrom somehow
+            - Greg will add his bootrom to the repo
+    - There was a question on how to generate header files without rebuilding the HW
+        - ‘make software’ will do this
+    - Issue with makefile failing CI for building documentation, requires pandoc; option to remove or install pandoc on the CI machine; Florian will install pandoc
+    - Completion of QuickLogic/CMC/Synopsys licensing is imminent; synthesis and hand-off to back-end design will begin soon; deadline for Fall tapeout is end of October
+- CORE-V-MCU committer discussion
+    - Duncan identified 5 things to do from perspective of managing the program
+        - 1) documenting the branch strategy; dev and master branch in core-v-mcu repo
+        - 2) committer training, roles in Eclipse project
+        - 3) committer elections; Greg and Tim are both committers
+        - 4) bring project under Eclipse umbrella and CORE-V-CORES umbrella
+        - 5) plan approved gate; review checklist, documentation; project freeze checklist
+    - Agreed to meet August 25 at 1pm EDT to discuss; Hugh will send Teams meeting invite