Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Cores TG december #490

Merged
merged 1 commit into from
Dec 15, 2021
Merged

Cores TG december #490

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
33 changes: 33 additions & 0 deletions cores/MeetingMinutes/December.06.2021.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
# Cores TG Meeting, December 6, 2021

## Attendees
* J�r�me Quevremont (Thales)
* Arjan Bink (Silicon Labs)
* Oystein Knauserud (Silicon Labs)
* Davide Schiavone (OpenHW)
* Duncan Bees (OpenHW)
* Jean-Luc Nagel (CSEM)
* Pascal Gouedo (Dolphin)
* Yoann Pruvost
* Tariq Kurd (Huawei)
* Ibrahim Abu Kharmeh (Huawei)

## CV32E40P 'v2'

Pascal gave an update on the CV32E40P status. Project Launch (PL) was presented in the TWG in November.

## CV32E40X / CV32E40S

Oystein gave an update on the CV32E40X / CV32E40S status. Write buffer implementation is complete. Data independent timing and dummy instruction insertion work for the CV32E40S is in progress. Formal verification is still considered a bottleneck.

## CV32E41P

Tariq Kurd presented the CV32E41P status. Zfinx has been implemented and Zce is almost implemented.

## CVA6

J�r�me Quevremont gave an update on the CVA6.

## Cores TG specific feedback from OpenHW members survey

Discussed Cores TG specific feedback.
Binary file added cores/MeetingPresentations/Cores-TG-12.06.2021.pdf
View file
Open in desktop
Binary file not shown.