Core-V MCU UVM Environment Project Proposal

[datum-dpoulin]

This is the documents for the project proposal for a UVM Environment for the core-v-mcu.

[DBees]

Nice work and great diagram, thank you for adding the diagram.

High Level Summary of project, project components, and deliverables

Maybe add a 1 sentence statement of what the project adds in terms of new capabilities. That is extend the sentence "The verification environment will follow..." AND WILL ALLOW ......

Can you explain what you mean by "software driven verification"?

Verification of all the peripherals: can you list out as examples one or more MCU peripherals and explain the approach to verification using that example(s)? Perhaps a 1 paragraph description of how verification will proceed for that example(s)?

Do we need models for these peripherals and do we have those models? If not, what do we need to do to get them?

Rather than TBD, it is preferable to put a stake in the ground about when you'll come back to the TWG for Project Launch. Conceptually not that much more than PC, but for PL you'll need a more full feature list and preliminary project plan (not a full project plan). I'd recommend to target 3 months from now. (Otherwise, the PC phase can tend to drag on indefinitely)

[MikeOpenHWGroup]

Do we need models for these peripherals

@DBees, you are correct. In order to verify the peripherals, the verification environment (testbench) will require some sort of model of each peripheral. The "completeness" of these peripheral models will vary, depending on the peripheral and be determined when the DVplan is complete. I do not think this level of detail is warranted for a PC.

do we have those models?

No, these models to not yet exist.

what do we need to do to get them?

The models will be coded in SystemVerilog and integrated into the predictor component of the environment. Part of the effort of completing this project will be developing this predictor.

[DBees]

I would recommend that the requirement for these models can be mentioned in the PC since we know that and impacts the scope of the project.

[MikeOpenHWGroup]

OK, I'm sensing that small tweaks around the edges of the PC are not working for us. So how about something like this:

Known market/project requirements at PC gate

• A UVM verification environment that can:
  • Fully verify the CORE-V MCU peripherals and connectivity to TRL-5.
  • Be extended to verify future versions of the MCU including devices with new/different peripherals and topology.
  • Support a self-checking environment using extensible prediction and scoreboarding components.
  • Replace the core with UVM bus agent(s) (e.g. OBI) to drive stimulus and collect responses sufficient to achieve above.
• Ability to simulate with Xilinx Vivado.
• Verification (to TRL-5) of the following CORE-V MCU peripherals:
  • uDMA
  • SPI
  • QSPI
  • UART
  • I2C
  • JTAG
  • CPI
  • SDIO

[DBees]

perfect

[MikeOpenHWGroup]

Awesome. @datum-dpoulin, can you push in an update to the mcu_uvm_project_concept.md with the above update? Thanks!

[datum-dpoulin]

Will do

…

On Fri, Jan 28, 2022 at 4:13 PM Mike Thompson ***@***.***> wrote: Awesome. @datum-dpoulin <https://github.com/datum-dpoulin>, can you push in an update to the mcu_uvm_project_concept.md with the above update? Thanks! — Reply to this email directly, view it on GitHub <#504 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ANHGK7ZXDH4AEDTLC64YBPDUYMBHLANCNFSM5MWM6A7Q> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[datum-dpoulin]

Ok I've made the changes

[datum-dpoulin]

@DBees What is the next step to get this thing through?