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8346664: C2: Optimize mask check with constant offset #22856

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@mernst-github mernst-github commented Dec 21, 2024

Fixes JDK-8346664: extends the optimization of masked sums introduced in #6697 to cover constant values, which currently break the optimization.

Such constant values arise in an expression of the following form, for example from MemorySegmentImpl#isAlignedForElement:

(base + (index + 1) << 8) & 255
=> MulNode
(base + (index << 8 + 256)) & 255
=> AddNode
((base + index << 8) + 256) & 255

Currently, 256 is not being recognized as a shifted value. This PR enables further reduction:

((base + index << 8) + 256) & 255
=> MulNode (this PR)
(base + index << 8) & 255
=> MulNode (PR #6697)
base & 255 (loop invariant)

Implementation notes:

  • in order to stay with the flow of the current implementation, I refrained from solving general (const & mask)==0 cases, but only those where const == _ << shift.
  • I modified existing test cases adding/subtracting from the index var (which would fail with current C2). Let me know if would like to see separate cases for these.
  • I verified that the originating issue "scaled varhandle indexed with i+1" (https://mail.openjdk.org/pipermail/panama-dev/2024-December/020835.html) is resolved with this PR.

Progress

  • Change must be properly reviewed (1 review required, with at least 1 Reviewer)
  • Change must not contain extraneous whitespace
  • Commit message must refer to an issue

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 ⚠️ OCA signatory status must be verified

Issue

  • JDK-8346664: C2: Optimize mask check with constant offset (Enhancement - P4)

Reviewing

Using git

Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/22856/head:pull/22856
$ git checkout pull/22856

Update a local copy of the PR:
$ git checkout pull/22856
$ git pull https://git.openjdk.org/jdk.git pull/22856/head

Using Skara CLI tools

Checkout this PR locally:
$ git pr checkout 22856

View PR using the GUI difftool:
$ git pr show -t 22856

Using diff file

Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/22856.diff

Extends the optimization of masked sums introduced in openjdk#6697 to cover constant values, which currently break the optimization.

Such constant values arise in an expression of the following form, for example from MemorySegmentImpl#isAlignedForElement:

(base + (index + 1) << 8) & 255
=> MulNode
(base + (index << 8 + 256)) & 255
=> AddNode
((base + index << 8) + 256) & 255

Currently, "256" is not being recognized as a shifted value. This PR enables:

((base + index << 8) + 256) & 255
=> MulNode
(base + index << 8) & 255
=> MulNode (PR openjdk#6697)
base & 255
@bridgekeeper bridgekeeper bot added the oca Needs verification of OCA signatory status label Dec 21, 2024
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@mernst-github The following label will be automatically applied to this pull request:

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@mernst-github mernst-github changed the title 8346664: C2: optimize constant addends in masked sums 8346664: C2: Optimize mask check with constant offset Dec 21, 2024
@@ -2052,94 +2052,88 @@ const Type* RotateRightNode::Value(PhaseGVN* phase) const {
}
}

// Given an expression (AndX shift mask) or (AndX mask shift),
// Returns a lower bound of the number of trailing zeros in expr.
jint MulNode::AndIL_min_trailing_zeros(PhaseGVN* phase, Node* expr, BasicType bt) {
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This could be a static function, I don't see much value in it being a method in MulNode.

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@mernst-github mernst-github Dec 24, 2024

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// Returns a lower bound of the number of trailing zeros in expr.
jint MulNode::AndIL_min_trailing_zeros(PhaseGVN* phase, Node* expr, BasicType bt) {
expr = expr->uncast();
if (expr == nullptr) {
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This should not be nullptr, you can safely remove it.

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if (type->is_con()) {
long con = type->get_con_as_long(type->basic_type());
return con == 0L ? 0 : count_trailing_zeros(con);
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For the sake of consistency, we should return the type width for con == 0, you can obtain this by type2aelementbytes(bt) * 8

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if (expr->Opcode() == Op_ConvI2L) {
expr = expr->in(1);
if (expr == nullptr) {
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This cannot be nullptr, you can safely remove it, the same for expr->uncast() below. In general, the only case when the input of a ConvI2L (and other nodes) not being an int is when it is top, which means it is empty. A.k.a unreachable code.

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if (expr == nullptr) {
return 0;
}
type = phase->type(expr)->isa_int();
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You are trying to look through a ConvI2L, I think for the sake of consistency, you can reassign bt to T_INT at this point.

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return 0;
}
const TypeInt* rhs_t = phase->type(rhs)->isa_int();
if (!rhs_t || !rhs_t->is_con()) {
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We are trying to avoid implicit conversion to bool, you can use an explicit rhs_t != nullptr here.

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if (!rhs_t || !rhs_t->is_con()) {
return 0;
}
return rhs_t->get_con() & ((type->isa_int() ? BitsPerJavaInteger : BitsPerJavaLong) - 1);
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If you reassign bt, you can do type2aelementbytes(bt), which IMO is clearer.

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bool MulNode::AndIL_shift_and_mask_is_always_zero(PhaseGVN* phase, Node* shift, Node* mask, BasicType bt, bool check_reverse) {
if (mask == nullptr || shift == nullptr) {
// mask M, we check for both operand orders.
bool MulNode::AndIL_is_always_zero(PhaseGVN* phase, Node* expr, Node* mask, BasicType bt, bool check_reverse) {
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Actually you cannot conclude that ((x + y) & m) == 0 iff (x & m) == 0 when (y & m) == 0 because the addition x + y can carry some bit into the positions at which m is set. Consider this example for illustration:

(0b1010 + 0b0010) & 0b0100 == 0b1100 & 0b0100 == 0b0100 != 0

even when

0b1010 & 0b0100 == 0
0b0010 & 0b0100 == 0

The most trivial sufficient condition we are using here is that the lowest bit set of y is larger than the highest bit set of m. Because then adding y into x does not carry any bit into the result that is set in m but not set in x. This method can be a static function, too IMO.

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@@ -120,7 +120,7 @@ public static void checkShiftNonConstMaskLong(long res) {
@IR(counts = { IRNode.AND_I, "1" })
@IR(failOn = { IRNode.ADD_I, IRNode.LSHIFT_I })
public static int addShiftMaskInt(int i, int j) {
return (j + (i << 2)) & 3; // transformed to: return j & 3;
return (j + ((i + 1) << 2)) & 3; // transformed to: return j & 3;
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I would prefer you adding other test cases instead of modifying existing ones.

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* make helpers static
* remove null checks
* separate test cases
* naming / reword comments

readability:
* move reverse checks to (some) callsites
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@@ -2052,94 +2052,88 @@ const Type* RotateRightNode::Value(PhaseGVN* phase) const {
}
}

// Given an expression (AndX shift mask) or (AndX mask shift),
// Returns a lower bound of the number of trailing zeros in expr.
jint MulNode::AndIL_min_trailing_zeros(PhaseGVN* phase, Node* expr, BasicType bt) {
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// Returns a lower bound of the number of trailing zeros in expr.
jint MulNode::AndIL_min_trailing_zeros(PhaseGVN* phase, Node* expr, BasicType bt) {
expr = expr->uncast();
if (expr == nullptr) {
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if (expr->Opcode() == Op_ConvI2L) {
expr = expr->in(1);
if (expr == nullptr) {
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if (type->is_con()) {
long con = type->get_con_as_long(type->basic_type());
return con == 0L ? 0 : count_trailing_zeros(con);
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if (expr == nullptr) {
return 0;
}
type = phase->type(expr)->isa_int();
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return 0;
}
const TypeInt* rhs_t = phase->type(rhs)->isa_int();
if (!rhs_t || !rhs_t->is_con()) {
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if (!rhs_t || !rhs_t->is_con()) {
return 0;
}
return rhs_t->get_con() & ((type->isa_int() ? BitsPerJavaInteger : BitsPerJavaLong) - 1);
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bool MulNode::AndIL_shift_and_mask_is_always_zero(PhaseGVN* phase, Node* shift, Node* mask, BasicType bt, bool check_reverse) {
if (mask == nullptr || shift == nullptr) {
// mask M, we check for both operand orders.
bool MulNode::AndIL_is_always_zero(PhaseGVN* phase, Node* expr, Node* mask, BasicType bt, bool check_reverse) {
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Comment on lines +678 to +679
if (AndIL_is_zero_element(phase, in(1), in(2), T_INT) ||
AndIL_is_zero_element(phase, in(2), in(1), T_INT)) {
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@@ -120,7 +120,7 @@ public static void checkShiftNonConstMaskLong(long res) {
@IR(counts = { IRNode.AND_I, "1" })
@IR(failOn = { IRNode.ADD_I, IRNode.LSHIFT_I })
public static int addShiftMaskInt(int i, int j) {
return (j + (i << 2)) & 3; // transformed to: return j & 3;
return (j + ((i + 1) << 2)) & 3; // transformed to: return j & 3;
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