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8297445: PPC64: Represent Registers as values
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Reviewed-by: mbaesken
Backport-of: 9c77e41b81ebd28bd92ea7adad605981a5519046
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TheRealMDoerr committed May 13, 2024
1 parent 20c2511 commit 16579f8
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Showing 15 changed files with 395 additions and 698 deletions.
4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -1919,7 +1919,7 @@ class Assembler : public AbstractAssembler {

// More convenient version.
int condition_register_bit(ConditionRegister cr, Condition c) {
return 4 * (int)(intptr_t)cr + c;
return 4 * cr.encoding() + c;
}
void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -589,7 +589,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
case Bytecodes::_f2i: {
bool dst_in_memory = !VM_Version::has_mtfprd();
FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
Label L;
// Result must be 0 if value is NaN; test by comparing value to itself.
__ fcmpu(CCR0, rsrc, rsrc);
Expand All @@ -613,7 +613,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
case Bytecodes::_f2l: {
bool dst_in_memory = !VM_Version::has_mtfprd();
FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
Label L;
// Result must be 0 if value is NaN; test by comparing value to itself.
__ fcmpu(CCR0, rsrc, rsrc);
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -540,15 +540,15 @@ class ZSetupArguments {

if (_ref != R4_ARG2) {
// Calculate address first as the address' base register might clash with R4_ARG2
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base());
__ addi(R4_ARG2, _ref_addr.base(), _ref_addr.disp());
__ mr_if_needed(R3_ARG1, _ref);
} else if (_ref_addr.base() != R3_ARG1) {
__ mr(R3_ARG1, _ref);
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base()); // Cloberring _ref
__ addi(R4_ARG2, _ref_addr.base(), _ref_addr.disp()); // Clobbering _ref
} else {
// Arguments are provided in inverse order (i.e. _ref == R4_ARG2, _ref_addr == R3_ARG1)
__ mr(R0, _ref);
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base());
__ addi(R4_ARG2, _ref_addr.base(), _ref_addr.disp());
__ mr(R3_ARG1, R0);
}
}
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -1779,7 +1779,7 @@ void InterpreterMacroAssembler::profile_arguments_type(Register callee,
if (MethodData::profile_arguments()) {
Label done;
int off_to_args = in_bytes(TypeEntriesAtCall::args_data_offset());
add(R28_mdx, off_to_args, R28_mdx);
addi(R28_mdx, R28_mdx, off_to_args);

for (int i = 0; i < TypeProfileArgsLimit; i++) {
if (i > 0 || MethodData::profile_return()) {
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/methodHandles_ppc.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -300,7 +300,7 @@ address MethodHandles::generate_method_handle_interpreter_entry(MacroAssembler*
}
Register R19_member = R19_method; // MemberName ptr; incoming method ptr is dead now
__ ld(R19_member, RegisterOrConstant((intptr_t)8), R15_argbase);
__ add(R15_argbase, Interpreter::stackElementSize, R15_argbase);
__ addi(R15_argbase, R15_argbase, Interpreter::stackElementSize);
generate_method_handle_dispatch(_masm, iid, tmp_recv, R19_member, not_for_compiler_entry);
}

Expand Down
37 changes: 0 additions & 37 deletions src/hotspot/cpu/ppc/register_definitions_ppc.cpp

This file was deleted.

29 changes: 14 additions & 15 deletions src/hotspot/cpu/ppc/register_ppc.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand All @@ -26,8 +26,7 @@
#include "precompiled.hpp"
#include "register_ppc.hpp"


const char* RegisterImpl::name() const {
const char* Register::name() const {
const char* names[number_of_registers] = {
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
Expand All @@ -37,14 +36,14 @@ const char* RegisterImpl::name() const {
return is_valid() ? names[encoding()] : "noreg";
}

const char* ConditionRegisterImpl::name() const {
const char* ConditionRegister::name() const {
const char* names[number_of_registers] = {
"CR0", "CR1", "CR2", "CR3", "CR4", "CR5", "CR6", "CR7"
};
return is_valid() ? names[encoding()] : "cnoreg";
}

const char* FloatRegisterImpl::name() const {
const char* FloatRegister::name() const {
const char* names[number_of_registers] = {
"F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
"F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
Expand All @@ -54,14 +53,14 @@ const char* FloatRegisterImpl::name() const {
return is_valid() ? names[encoding()] : "fnoreg";
}

const char* SpecialRegisterImpl::name() const {
const char* SpecialRegister::name() const {
const char* names[number_of_registers] = {
"SR_XER", "SR_LR", "SR_CTR", "SR_VRSAVE", "SR_SPEFSCR", "SR_PPR"
};
return is_valid() ? names[encoding()] : "snoreg";
}

const char* VectorRegisterImpl::name() const {
const char* VectorRegister::name() const {
const char* names[number_of_registers] = {
"VR0", "VR1", "VR2", "VR3", "VR4", "VR5", "VR6", "VR7",
"VR8", "VR9", "VR10", "VR11", "VR12", "VR13", "VR14", "VR15",
Expand All @@ -71,7 +70,7 @@ const char* VectorRegisterImpl::name() const {
return is_valid() ? names[encoding()] : "vnoreg";
}

const char* VectorSRegisterImpl::name() const {
const char* VectorSRegister::name() const {
const char* names[number_of_registers] = {
"VSR0", "VSR1", "VSR2", "VSR3", "VSR4", "VSR5", "VSR6", "VSR7",
"VSR8", "VSR9", "VSR10", "VSR11", "VSR12", "VSR13", "VSR14", "VSR15",
Expand All @@ -86,19 +85,19 @@ const char* VectorSRegisterImpl::name() const {
}

// Method to convert a FloatRegister to a Vector-Scalar Register (VectorSRegister)
VectorSRegister FloatRegisterImpl::to_vsr() const {
if (this == fnoreg) { return vsnoreg; }
VectorSRegister FloatRegister::to_vsr() const {
if (*this == fnoreg) { return vsnoreg; }
return as_VectorSRegister(encoding());
}

// Method to convert a VectorRegister to a Vector-Scalar Register (VectorSRegister)
VectorSRegister VectorRegisterImpl::to_vsr() const {
if (this == vnoreg) { return vsnoreg; }
VectorSRegister VectorRegister::to_vsr() const {
if (*this == vnoreg) { return vsnoreg; }
return as_VectorSRegister(encoding() + 32);
}

// Method to convert a VectorSRegister to a Vector Register (VectorRegister)
VectorRegister VectorSRegisterImpl::to_vr() const {
if (this == vsnoreg) { return vnoreg; }
VectorRegister VectorSRegister::to_vr() const {
if (*this == vsnoreg) { return vnoreg; }
return as_VectorRegister(encoding() - 32);
}
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