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Detect SHA extensions #12549

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Detect SHA extensions #12549

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6e38215
Detect SHA extensions
cybojanek Sep 5, 2021
9fde75d
Add icp algorithm implementation selector
cybojanek Sep 6, 2021
737f67e
Initialize sha2 module with existing implementations
cybojanek Sep 6, 2021
733860f
Add SHA256 and SHA512 fast implementations
cybojanek Sep 6, 2021
666cc61
Fix SHA 2 transform function signatures
cybojanek Jan 12, 2022
310811a
Fix SHA 2 impl const usage
cybojanek Jan 12, 2022
8969a46
Surround SHA 2 usage with kfpu_begin and kfpu_end
cybojanek Jan 12, 2022
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1 change: 1 addition & 0 deletions COPYRIGHT
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ notable exceptions and their respective licenses include:
* AES Implementation: module/icp/asm-x86_64/aes/THIRDPARTYLICENSE.gladman
* AES Implementation: module/icp/asm-x86_64/aes/THIRDPARTYLICENSE.openssl
* PBKDF2 Implementation: lib/libzfs/THIRDPARTYLICENSE.openssl
* SHA2 Implementation: module/icp/asm-x86_64/sha2/THIRDPARTYLICENSE.intel
* SPL Implementation: module/os/linux/spl/THIRDPARTYLICENSE.gplv2
* GCM Implementation: module/icp/asm-x86_64/modes/THIRDPARTYLICENSE.cryptogams
* GCM Implementation: module/icp/asm-x86_64/modes/THIRDPARTYLICENSE.openssl
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2 changes: 2 additions & 0 deletions Makefile.am
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Expand Up @@ -43,6 +43,8 @@ EXTRA_DIST += module/icp/asm-x86_64/modes/THIRDPARTYLICENSE.cryptogams
EXTRA_DIST += module/icp/asm-x86_64/modes/THIRDPARTYLICENSE.cryptogams.descrip
EXTRA_DIST += module/icp/asm-x86_64/modes/THIRDPARTYLICENSE.openssl
EXTRA_DIST += module/icp/asm-x86_64/modes/THIRDPARTYLICENSE.openssl.descrip
EXTRA_DIST += module/icp/asm-x86_64/sha2/THIRDPARTYLICENSE.intel
EXTRA_DIST += module/icp/asm-x86_64/sha2/THIRDPARTYLICENSE.intel.descrip
EXTRA_DIST += module/os/linux/spl/THIRDPARTYLICENSE.gplv2
EXTRA_DIST += module/os/linux/spl/THIRDPARTYLICENSE.gplv2.descrip
EXTRA_DIST += module/zfs/THIRDPARTYLICENSE.cityhash
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22 changes: 22 additions & 0 deletions config/toolchain-simd.m4
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Expand Up @@ -24,6 +24,7 @@ AC_DEFUN([ZFS_AC_CONFIG_ALWAYS_TOOLCHAIN_SIMD], [
ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_AES
ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_PCLMULQDQ
ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_MOVBE
ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_SHA
;;
esac
])
Expand Down Expand Up @@ -422,3 +423,24 @@ AC_DEFUN([ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_MOVBE], [
AC_MSG_RESULT([no])
])
])

dnl #
dnl # ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_SHA
dnl #
AC_DEFUN([ZFS_AC_CONFIG_TOOLCHAIN_CAN_BUILD_SHA], [
AC_MSG_CHECKING([whether host toolchain supports SHA])

AC_LINK_IFELSE([AC_LANG_SOURCE([
[
void main()
{
__asm__ __volatile__("sha1msg1 %xmm0, %xmm1");
__asm__ __volatile__("sha256msg1 %xmm0, %xmm1");
}
]])], [
AC_MSG_RESULT([yes])
AC_DEFINE([HAVE_SHA], 1, [Define if host toolchain supports SHA])
], [
AC_MSG_RESULT([no])
])
])
13 changes: 13 additions & 0 deletions include/os/linux/kernel/linux/simd_x86.h
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Expand Up @@ -490,6 +490,19 @@ zfs_movbe_available(void)
#endif
}

/*
* Check if SHA instruction is available
*/
static inline boolean_t
zfs_sha_available(void)
{
#if defined(X86_FEATURE_SHA_NI)
return (!!boot_cpu_has(X86_FEATURE_SHA_NI));
#else
return (B_FALSE);
#endif
}

/*
* AVX-512 family of instruction sets:
*
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9 changes: 8 additions & 1 deletion lib/libicp/Makefile.am
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Expand Up @@ -19,7 +19,13 @@ ASM_SOURCES_AS = \
asm-x86_64/modes/ghash-x86_64.S \
asm-x86_64/sha1/sha1-x86_64.S \
asm-x86_64/sha2/sha256_impl.S \
asm-x86_64/sha2/sha512_impl.S
asm-x86_64/sha2/sha256_avx.S \
asm-x86_64/sha2/sha256_ssse3.S \
asm-x86_64/sha2/sha256_ni.S \
asm-x86_64/sha2/sha512_impl.S \
asm-x86_64/sha2/sha512_avx.S \
asm-x86_64/sha2/sha512_avx2.S \
asm-x86_64/sha2/sha512_ssse3.S
else
ASM_SOURCES_C =
ASM_SOURCES_AS =
Expand All @@ -38,6 +44,7 @@ KERNEL_C = \
algs/aes/aes_impl.c \
algs/aes/aes_modes.c \
algs/edonr/edonr.c \
algs/impl/impl.c \
algs/modes/modes.c \
algs/modes/cbc.c \
algs/modes/gcm_generic.c \
Expand Down
15 changes: 14 additions & 1 deletion lib/libspl/include/sys/simd.h
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Expand Up @@ -78,7 +78,8 @@ typedef enum cpuid_inst_sets {
AVX512VL,
AES,
PCLMULQDQ,
MOVBE
MOVBE,
SHA,
} cpuid_inst_sets_t;

/*
Expand All @@ -103,6 +104,7 @@ typedef struct cpuid_feature_desc {
#define _AES_BIT (1U << 25)
#define _PCLMULQDQ_BIT (1U << 1)
#define _MOVBE_BIT (1U << 22)
#define _SHA_BIT (1U << 29)

/*
* Descriptions of supported instruction sets
Expand Down Expand Up @@ -131,6 +133,7 @@ static const cpuid_feature_desc_t cpuid_features[] = {
[AES] = {1U, 0U, _AES_BIT, ECX },
[PCLMULQDQ] = {1U, 0U, _PCLMULQDQ_BIT, ECX },
[MOVBE] = {1U, 0U, _MOVBE_BIT, ECX },
[SHA] = {7U, 0U, _SHA_BIT, EBX },
};

/*
Expand Down Expand Up @@ -204,6 +207,7 @@ CPUID_FEATURE_CHECK(avx512vl, AVX512VL);
CPUID_FEATURE_CHECK(aes, AES);
CPUID_FEATURE_CHECK(pclmulqdq, PCLMULQDQ);
CPUID_FEATURE_CHECK(movbe, MOVBE);
CPUID_FEATURE_CHECK(sha, SHA);

/*
* Detect register set support
Expand Down Expand Up @@ -345,6 +349,15 @@ zfs_movbe_available(void)
return (__cpuid_has_movbe());
}

/*
* Check if SHA instruction is available
*/
static inline boolean_t
zfs_sha_available(void)
{
return (__cpuid_has_sha());
}

/*
* AVX-512 family of instruction sets:
*
Expand Down
8 changes: 8 additions & 0 deletions module/icp/Makefile.in
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Expand Up @@ -43,6 +43,7 @@ $(MODULE)-objs += algs/aes/aes_impl_generic.o
$(MODULE)-objs += algs/aes/aes_impl.o
$(MODULE)-objs += algs/aes/aes_modes.o
$(MODULE)-objs += algs/edonr/edonr.o
$(MODULE)-objs += algs/impl/impl.o
$(MODULE)-objs += algs/sha1/sha1.o
$(MODULE)-objs += algs/sha2/sha2.o
$(MODULE)-objs += algs/skein/skein.o
Expand All @@ -57,7 +58,13 @@ $(MODULE)-$(CONFIG_X86_64) += asm-x86_64/modes/aesni-gcm-x86_64.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/modes/ghash-x86_64.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha1/sha1-x86_64.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha256_impl.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha256_avx.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha256_ssse3.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha256_ni.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha512_impl.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha512_avx.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha512_avx2.o
$(MODULE)-$(CONFIG_X86_64) += asm-x86_64/sha2/sha512_ssse3.o

$(MODULE)-$(CONFIG_X86) += algs/modes/gcm_pclmulqdq.o
$(MODULE)-$(CONFIG_X86) += algs/aes/aes_impl_aesni.o
Expand Down Expand Up @@ -86,6 +93,7 @@ ICP_DIRS = \
algs/aes \
algs/edonr \
algs/modes \
algs/impl \
algs/sha1 \
algs/sha2 \
algs/skein \
Expand Down
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