Verilog Analyzer

[adarsh200496]

Hey guys!
Has anyone here made an Analyzer for Verilog?

Thanks!

[duaneellissd]

+1 this would be a great addition
Also VHDL

[tarzanek]

@adarsh200496 @duaneellissd It should be easy to add, since ctags already supports both - have a look at history commits on adding new analyzers + feel free to ask (on slack or here)
(it's a matter of jflex lexical parsers definition since ctags supports both)

[tarzanek]

btw. writing an analyzer is fun, give it a shot guys! ;-)

[idodeclare]

Oops I didn't use "Resolve{s|d}", "Fix{es|ed}", or "Close{s|d}" in my commit message for auto-issue closing

[vladak]

Next time :-)