Merge pull request #55 from orangecrab-fpga/feature/update_r0.2.1

feature/update r0.2.1

README.md

@@ -2,12 +2,13 @@
 [OrangeCrab Web site](https://orangecrab-fpga.github.io/orangecrab-hardware/)
 
 ## ECP5 FPGA Feather development board.
-![Front Photo](documentation/hugo-files/static/r0.2/orangeCrab-12.jpg "Front Photo")
+![Front Photo](documentation/images/OrangeCrab_r0.2.1_front.jpeg "Front Photo")
 
 ## Latest Revision: 
-* [OrangeCrab r0.2](hardware/orangecrab_r0.2/)
+* [OrangeCrab r0.2.1](hardware/orangecrab_r0.2.1/)
 
 Previous Revisions:
+* [OrangeCrab r0.2](hardware/orangecrab_r0.2/)
 * [OrangeCrab r0.1](hardware/orangecrab_r0.1/)
 
 ---
@@ -16,7 +17,7 @@ Previous Revisions:
 There aren't many OSHW ECP5 boards available. Given that this FPGA is fully supported by an open source toolchain I decided to create one. In order to make use of the DDR3L support the ECP5 has, I've added some DDR3L memory. The board matches the feather format
 
 ## Hardware Overview
-* Lattice ECP5-25F FPGA in csfBGA285 package
+* Lattice ECP5-25F or ECP5-85F FPGA in csfBGA285 package
     * 24 K - Look Up Tables
     * 1008 Kb - Embedded Block RAM
     * 194 Kb - Distributed RAM
@@ -25,10 +26,10 @@ There aren't many OSHW ECP5 boards available. Given that this FPGA is fully supp
     * Internal oscillator
     * Flexible I/O for DDR3 Memory Support
 * DDR3L Memory
-    * 128 Mbytes (1Gbit)
-    * 64M x16
+    * 128 Mbytes (1Gbit) or 512Mbytes (4Gbit)
+    * x16 data width to FPGA
     * 1.35V low voltage operation
-* Micro USB connection
+* USB-C connection
     * Full-speed (12Mbit) USB with direct connection to FPGA
 * Non-volatile Storage
     * 128Mbit QSPI FLASH Memory 
@@ -43,7 +44,7 @@ There aren't many OSHW ECP5 boards available. Given that this FPGA is fully supp
     * Battery charger (100mA), with charge indicator LED
     * LiPo battery connector (PH type) (1-cell: 3.7-4.2V)
 * 48MHz onboard oscillator
-* Standard 0.05" JTAG connector
+* Accessible 0.1" JTAG breakout
 * User I/O
     * 1x Button 
     * 1x RGB LED
@@ -56,10 +57,10 @@ There aren't many OSHW ECP5 boards available. Given that this FPGA is fully supp
     * Battery voltage sensing
 * Feather Format Board
     * Dimensions: 22.86mm x 50.8mm (0.9" x 2.0")
-
+    * Castellated I/O edges
 ---
 
-![Back Photo](documentation/hugo-files/static/r0.2/orangeCrab-4.jpg "Back Photo")
+![Back Photo](documentation/images/OrangeCrab_r0.2.1_back.jpeg "Back Photo")
 
 ## Example code
 Example code for Verilog, Litex, And RiscV can be found here:

documentation/hugo-files/config.toml

@@ -1,11 +1,11 @@
 baseURL = "https://orangecrab-fpga.github.io/orangecrab-hardware"
 languageCode = "en-us"
-title = "OrangeCrab Docs"
+title = "OrangeCrab"
 theme = "book"
 themesDir = "./themes"
 
 enableGitInfo = true
-disableKinds = ['taxonomy', 'taxonomyTerm']
+disableKinds = ['taxonomy']
 
 
 [params]
@@ -15,7 +15,7 @@ disableKinds = ['taxonomy', 'taxonomyTerm']
   BookSection = 'docs'
   BookDateFormat = 'Jan 2, 2006'
   BookSearch = true
-  BookLogo = 'crab.svg'
+
 
 [params.footer]
 	copyright = "[gregdavill](https://twitter.com/gregdavill)"

documentation/hugo-files/content/r0.2/docs/overview.md → documentation/hugo-files/content/_index.md

@@ -1,10 +1,12 @@
 ---
-title: Overview
+title: Introduction
 type: docs
 rev: r0.2
 ---
 
-# Overview
+![OrangeCrab Photo](docs/r0.2/orangeCrab-6.jpg "OrangeCrab Photo")
+
+# Introduction
 
 The OrangeCrab is a small pocket sized development board in the Adafruit feather format. While small in size it packs a punch! The standard version is equiped with a Lattice ECP5 FPGA, and DDR3L memory. Paired with the FPGA is a FLASH chip, with enough memory to store multiple bitstreams.
 
@@ -16,3 +18,38 @@ There is DDR3L memory attached to the FPGA. The hardware is configured by defaul
 
 ## USB
 The micro usb connector is wired directly into the FPGA. Just as a microprocessor can emulate UART or SPI using standard I/O pins the FPGA can do the same for USB. By using some of the FPGA logic to create a USB core, we can use the I/O pins on the FPGA to act as a USB device. This will operate at USB 2.0 full-speed rates (12Mbit/s). Operating at High Speed rates (480Mbit/s) is not possible with the OrangeCrab hardware.
+
+## Hardware Versions
+
+There are currently 3 released version of the board:
+
+{{< hint warning >}}
+### [Hardware r0.1]({{< relref "/docs/r0.1.md" >}})
+Status: Prototype only
+
+        Standout Features:
+        - 2MByte FLASH 2x3mm USON part
+        - ATSAMD10/11 Co-processor planned mainly for the ADC/DAC (fw never written)
+        - Expansion port on the bottom of the feather breaking out extra I/O differential pairs.
+{{< /hint >}}
+
+{{< hint warning >}}
+### [Hardware r0.2]({{< relref "/docs/r0.2.md" >}})
+Status: Superseded
+
+        Changes from r0.1:
+        - Added FPGA I/O based ADC
+        - Add User Button and self-reset
+        - Larger FLASH 2MBytes -> 16MBytes
+{{< /hint >}}
+
+{{< hint info >}}
+### [Hardware r0.2.1]({{< relref "/docs/r0.2.1.md" >}})
+Status: Currently produced design
+
+        Changes from r0.2:
+        - Changed USB micro-b to USB-C
+        - Swapped DCDC devices
+        - Added support for ECP5 85F-5G
+        - Added Castellated I/O pins 
+{{< /hint >}}

documentation/hugo-files/content/docs/downloads.md

@@ -0,0 +1,21 @@
+---
+title: Downloads
+type: docs
+rev: r0.2
+---
+
+# Downloads
+---
+
+## KiCad Sources
+[OrangeCrab GitHub Repository](http://github.com/gregdavill/OrangeCrab)
+
+## Other
+ * [Interactive HTML Bill Of Materials](../r0.2/OrangeCrab-r0.2-ibom.html)
+
+ * [Schematic (PDF)](https://github.com/gregdavill/OrangeCrab/raw/main/hardware/orangecrab_r0.2/Production/OrangeCrab-r0.2-sch.pdf)
+
+ * [Board CAD model (STEP)](https://github.com/gregdavill/OrangeCrab/raw/main/hardware/orangecrab_r0.2/Production/OrangeCrab-r0.2.step)
+
+ * [Production Gerbers (ZIP)](https://github.com/gregdavill/OrangeCrab/raw/main/hardware/orangecrab_r0.2/Production/OrangeCrab-r0.2-gerbers-20200126_122805.zip)
+

documentation/hugo-files/content/docs/pinout.md

@@ -0,0 +1,10 @@
+---
+title: Pinout
+type: docs
+rev: r0.2
+---
+
+# Pinout
+
+[![Pinout](../r0.2/OrangeCrab_r0.2_pinout.png "Pinout")](../r0.2/OrangeCrab_r0.2_pinout.png)
+Click for larger version

documentation/hugo-files/content/r0.1/_index.md → documentation/hugo-files/content/docs/r0.1.md

@@ -4,12 +4,6 @@ type: docs
 rev: r0.1
 ---
 
-# Introduction
-
-The OrangeCrab is an FPGA development board based around the Lattice ECP5 FPGA. The OrangeCrab features a direct USB connection to the FPGA and comes loaded with a DFU bootloader so you can get started without the need of an external programmer.
-
-The OrangeCrab makes use of the logic inside the ECP5 to support DDR3L memory. In it's minimal configuration this adds 128Mbytes of memory to the FPGA. Example gateware is provided that creates a System-On-Chip inside the FPGA with this RAM memory mapped.
-
 ## Technical details
 
 Here are the main details for the OrangeCrab

documentation/hugo-files/content/docs/r0.2.1.md

@@ -0,0 +1,56 @@
+---
+title: Introduction
+type: docs
+rev: r0.2
+---
+
+![Front Photo](OrangeCrab_r0.2.1_front.jpeg "Front Photo")
+
+## Technical details
+
+Here are the main details for the OrangeCrab (25F/85F)
+* Lattice ECP5-25F or ECP5-85F FPGA in csfBGA285 package
+    * 24 K - Look Up Tables
+    * 1008 Kb - Embedded Block RAM
+    * 194 Kb - Distributed RAM
+    * 28 - 18x18 Multipliers
+    * PLLs: 2
+    * Internal oscillator
+    * Flexible I/O for DDR3 Memory Support
+* DDR3L Memory
+    * 128 Mbytes (1Gbit) or 512Mbytes (4Gbit)
+    * x16 data width to FPGA
+    * 1.35V low voltage operation
+* USB-C connection
+    * Full-speed (12Mbit) USB with direct connection to FPGA
+* Non-volatile Storage
+    * 128Mbit QSPI FLASH Memory 
+        * Bootloader (First 4Mbits)
+        * User Bitstream
+        * User storage (Firmware/MSC backend/etc)
+        * QSPI compatible
+    * MicroSD socket
+        * 4bit SD interface (CK, CMD, DAT0-3)
+* Power supply
+    * High effeciency DCDC for main supplies
+    * Battery charger (100mA), with charge indicator LED
+    * LiPo battery connector (PH type) (1-cell: 3.7-4.2V)
+* 48MHz onboard oscillator
+* Accesible 0.1" JTAG breakout
+* User I/O
+    * 1x Button 
+    * 1x RGB LED
+    * 20x I/O on 0.1" headers
+* Analog System
+    * Analog Mux
+    * SAR ADC, external RC / input comparator of FPGA
+    * Digital bypass
+    * Internal channels for supply monitor
+    * Battery voltage sensing
+* Feather Format Board
+    * Dimensions: 22.86mm x 50.8mm (0.9" x 2.0")
+    * Castellated I/O edges
+
+## Photos
+![Front Photo](OrangeCrab_r0.2.1_front.jpeg "Front Photo")
+![Back Photo](OrangeCrab_r0.2.1_back.jpeg "Back Photo")

documentation/hugo-files/content/r0.2/_index.md → documentation/hugo-files/content/docs/r0.2.md

@@ -4,17 +4,6 @@ type: docs
 rev: r0.2
 ---
 
-# Introduction
-
-The OrangeCrab is an electronics development board. It is FPGA based featuring an ECP5 from Lattice. The board follows the slim [feather board specification](https://learn.adafruit.com/adafruit-feather/feather-specification) from Adafruit. The FPGA is compatible with all opensource toolchains and is perfect for experimenting with RISC-V cores. There aren't many FPGA boards available that make use of the ECP5, but here are some distinct features that set this broad apart:
-
-* Small Compact size (Take it anywhere!)
-* Direct USB connection to the FPGA (Operate as a DFU, MSC, CDC, or composite device!)
-* Onboard DDR3 Memory (1Gbit!)
-* Preloaded DFU bootloader (No external programmer required!)
-* It's Orange!
-
-
 ![Front Photo](orangeCrab-1.jpg "Front Photo")
 
 

documentation/hugo-files/content/menu/index.md

@@ -0,0 +1,12 @@
+---
+headless: true
+---
+
+- [Hardware]({{< relref "/" >}})
+  - [r0.1]({{< relref "/docs/r0.1.md" >}})
+  - [r0.2]({{< relref "/docs/r0.2.md" >}})
+  - [r0.2.1]({{< relref "/docs/r0.2.1.md" >}})
+- [Getting Started]({{< relref "/docs/getting started.md" >}})
+- [Pinout]({{< relref "/docs/pinout.md" >}})
+- [Downloads]({{< relref "/docs/downloads.md" >}})
+