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@CTSRD-CHERI Capability Hardware Enhanced RISC Instructions

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    292 repositories

    • S10FPGA

      Public
      Library containing Bluespec and Verilog components targetting Stratix 10 FPGAs
      Bluespec
      •0•1•0•0•Updated Oct 14, 2024Oct 14, 2024

    • cheribsd

      Public
      FreeBSD adapted for CHERI-RISC-V and Arm Morello.
      riscvchericheribsdmorellofreebsd
      C
      •
      Other
      •58•163•130•41•Updated Oct 14, 2024Oct 14, 2024

    • SIMTight

      Public
      Synthesisable SIMT-style RISC-V GPGPU
      haskellfpgariscvgpgpusimt
      Assembly
      •8•27•3•2•Updated Oct 14, 2024Oct 14, 2024

    • chericat

      Public
      C
      •
      Other
      •0•2•16•2•Updated Oct 12, 2024Oct 12, 2024

    • Toooba

      Public
      RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
      Bluespec
      •
      Other
      •36•21•4•2•Updated Oct 12, 2024Oct 12, 2024

    • qemu

      Public
      QEMU with support for CHERI
      C
      •
      Other
      •28•52•28•22•Updated Oct 10, 2024Oct 10, 2024

    • gdb

      Public
      The GNU debugger extended to support CHERI
      C
      •
      GNU General Public License v2.0
      •2•2•5•3•Updated Oct 10, 2024Oct 10, 2024

    • DE10Pro-cheri-bgas

      Public
      CHERI-BGAS DE10Pro quartus project
      Bluespec
      •1•0•1•1•Updated Oct 10, 2024Oct 10, 2024

    • cheri-demos

      Public
      HTML
      •0•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • de10pro-playground-user-scripts

      Public
      User scripts for the de10pro playground framework
      Python
      •0•0•0•0•Updated Oct 7, 2024Oct 7, 2024

    • sail-cheri-riscv

      Public
      CHERI-RISC-V model written in Sail
      Isabelle
      •
      Other
      •18•55•4•10•Updated Oct 7, 2024Oct 7, 2024

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •163•0•0•0•Updated Oct 7, 2024Oct 7, 2024

    • riscv-cheri

      Public
      This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      Python
      •
      Creative Commons Attribution 4.0 International
      •29•0•0•0•Updated Oct 4, 2024Oct 4, 2024

    • riscv-pk

      Public
      RISC-V Proxy Kernel
      C
      •
      Other
      •308•0•0•1•Updated Oct 3, 2024Oct 3, 2024

    • v8

      Public
      The official mirror of the V8 Git repository
      C++
      •
      Other
      •4k•0•0•1•Updated Oct 3, 2024Oct 3, 2024

    • cheribuild

      Public
      Easily build and run CHERI related projects
      Python
      •
      Other
      •45•65•30•15•Updated Oct 2, 2024Oct 2, 2024

    • fmem

      Public
      Tool to access FPGA memory on Stratix10
      C
      •0•0•0•0•Updated Oct 2, 2024Oct 2, 2024

    • libglvnd

      Public
      The GL Vendor-Neutral Dispatch library
      C
      •90•0•0•1•Updated Oct 1, 2024Oct 1, 2024

    • seL4

      Public
      The seL4 microkernel
      C
      •
      Other
      •664•2•0•0•Updated Sep 30, 2024Sep 30, 2024

    • jenkins-scripts

      Public
      Groovy
      •
      Other
      •1•3•0•0•Updated Sep 27, 2024Sep 27, 2024

    • TestRIG

      Public
      Testing processors with Random Instruction Generation
      Python
      •
      Other
      •8•29•6•2•Updated Sep 24, 2024Sep 24, 2024

    • QuickCheckVEngine

      Public
      A RISC-V TestRIG Verification Engine based on QuickCheck
      Haskell
      •
      BSD 2-Clause "Simplified" License
      •9•7•4•2•Updated Sep 24, 2024Sep 24, 2024

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. Forked from https://github.com/ivanmgribeiro-google/ibex
      SystemVerilog
      •
      Apache License 2.0
      •1•1•3•0•Updated Sep 24, 2024Sep 24, 2024

    • DE10Pro-softcore-devicetree

      Public
      devicetree description for a riscv core setup on DE10Pro
      Makefile
      •0•0•0•0•Updated Sep 19, 2024Sep 19, 2024

    • mrs

      Public
      CHERI malloc revocation shim (Obsolete! Use the version integrated into CheriBSD.)
      C
      •2•0•0•0•Updated Sep 18, 2024Sep 18, 2024

    • llvm-project

      Public
      Fork of LLVM adding CHERI support
      40•48•120•25•Updated Sep 17, 2024Sep 17, 2024

    • sail-morello-proofs

      Public
      Isabelle
      •
      Other
      •0•0•0•0•Updated Sep 13, 2024Sep 13, 2024

    • t-cheri

      Public
      Isabelle
      •
      Other
      •0•0•0•0•Updated Sep 13, 2024Sep 13, 2024

    • cheri-bgas-fuse-devfs

      Public
      A fuse filesystem to expose devices in the CHERI BGAS simulator
      C
      •0•0•0•0•Updated Sep 11, 2024Sep 11, 2024

    • BlueAXI4

      Public
      Bluespec
      •1•1•0•0•Updated Sep 11, 2024Sep 11, 2024