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    2 repositories

    • SWIS-V

      Public
      A Single Cycle RISC-V core supporting RV32I Instruction Set.
      Verilog
      •
      MIT License
      •2•0•0•0•Updated Jul 12, 2024Jul 12, 2024

    • Skill-Lab---RISCV

      Public
      0•0•0•0•Updated Jun 19, 2024Jun 19, 2024