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    18 repositories

    • IMU_sensor_demo

      Public
      Contains the files for PCB and Code for the demo of a ASM330LHHXG1 IMU sensor with Smartwave
      Python
      •0•0•0•0•Updated Oct 10, 2024Oct 10, 2024

    • tristan

      Public
      Verilog
      •0•1•6•0•Updated Sep 6, 2024Sep 6, 2024

    • wfg-API

      Public
      Python
      •
      Other
      •0•2•1•0•Updated Jun 19, 2024Jun 19, 2024

    • SmartWave_demos

      Public
      This repository includes the primary demo configuration files and relevant datasheets.
      Python
      •0•1•0•0•Updated May 28, 2024May 28, 2024

    • wfg-doc

      Public
      Documentation for waveform generator (SmartWave)
      0•0•0•0•Updated May 15, 2024May 15, 2024

    • smartwave_uart

      Public
      Python
      •0•0•0•0•Updated May 3, 2024May 3, 2024

    • cv32e40x

      Public
      4 stage, in-order, compute RISC-V core based on the CV32E40P
      SystemVerilog
      •
      Other
      •53•0•0•0•Updated Apr 8, 2024Apr 8, 2024

    • stepper_demo

      Public
      Stepper Motor demo script for the EX-MotorShield8874
      C++
      •0•0•0•0•Updated Feb 29, 2024Feb 29, 2024

    • tristan-openframe

      Public
      The ASIC design for the Tristan project based on openframe
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 8, 2024Feb 8, 2024

    • motor-shield

      Public
      The DCC-EX Motor Shield is based on two H-bridge motor drivers with integrated current sensing feedback to drive inductive loads like relays, solenoids, DC and stepping motors.
      kicadarduino-shieldpcb-design
      0•5•0•0•Updated Jan 9, 2024Jan 9, 2024

    • tristan-asic

      Public
      The ASIC design for the Tristan project
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 5, 2023Dec 5, 2023

    • pmod-intermediary

      Public
      0•1•0•0•Updated Nov 1, 2023Nov 1, 2023

    • fstdumper

      Public
      Verilog VPI module to dump FST (Fast Signal Trace) databases
      waveformsystemverilogvpisimulatorverilog
      C
      •
      GNU General Public License v3.0
      •2•16•4•0•Updated Sep 19, 2023Sep 19, 2023

    • tristan-unified-access-page

      Public
      Unified Access Page for the TRISTAN project
      30•0•0•0•Updated Aug 24, 2023Aug 24, 2023

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •232•0•0•0•Updated Aug 19, 2022Aug 19, 2022

    • caravel_wfg

      Public
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Jul 21, 2022Jul 21, 2022

    • waveform-generator

      Public
      Waveform Generator
      SystemVerilog
      •
      Apache License 2.0
      •0•11•3•0•Updated Jul 18, 2022Jul 18, 2022

    • go.debug

      Public
      Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
      verificationedaverilogsystemveriloghdluvmtestbenchverilator
      SystemVerilog
      •3•10•0•0•Updated Oct 14, 2021Oct 14, 2021