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    • Experiments related to our FMCAD 2021 paper "Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition"
      C
      0510Updated Apr 13, 2022Apr 13, 2022
    • Python
      1120Updated Aug 18, 2021Aug 18, 2021
    • Single instruction checking for RIDECORE
      Verilog
      1400Updated Jun 2, 2021Jun 2, 2021
    • Verilog
      BSD 3-Clause "New" or "Revised" License
      31310Updated Feb 6, 2021Feb 6, 2021
    • Python-based workflow to generate QED modules from ISA/architecture specifications
      Verilog
      3320Updated Feb 6, 2021Feb 6, 2021
    • cosa2

      Public
      Next generation CoSA.
      C++
      Other
      0300Updated Jan 27, 2021Jan 27, 2021
    • Source files to reproduce the results shown for A-QED at DAC 2020
      C++
      3730Updated Jul 29, 2020Jul 29, 2020
    • Case studies
      Verilog
      2520Updated Jul 17, 2019Jul 17, 2019
    • Verilog functional model for PHY
      Python
      BSD 3-Clause "New" or "Revised" License
      6700Updated Jun 27, 2019Jun 27, 2019