constr translat, ric model, test updates

os-fpga · Mar 9, 2024 · 18f32f5 · 18f32f5
1 parent 82393df
commit 18f32f5
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Showing 26 changed files with 90 additions and 55 deletions.
diff --git a/FOEDAG_rs b/FOEDAG_rs
diff --git a/Makefile b/Makefile
@@ -160,14 +160,15 @@ test/batch: run-cmake-release
 ifeq ($(RAPTOR_PUB),1)
 else
  ./build/bin/raptor --batch --script tests/Testcases/and2_verilog/run_raptor.tcl
+ ./build/bin/raptor --batch --mute --script tests/Testcases/and2_2clks/run_raptor.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/and2_wio/run_raptor.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/oneff_wio/run_raptor.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/and2_compact/raptor.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/counter16/counter16.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/keep_test/raptor.tcl 
  ./build/bin/raptor --batch --mute --script tests/Testcases/trivial/test.tcl
  ./build/bin/raptor --batch --mute --script tests/Jira_Testcase/GEMINIEDA_96/build.tcl
- ./build/bin/raptor --batch --mute --script tests/Jira_Testcase/GEMINIEDA_107/dsp_mul_unsigned_reg/raptor.tcl --device 1GE75
+ ./build/bin/raptor --batch --mute --script tests/Jira_Testcase/GEMINIEDA_107/dsp_mul_unsigned_reg/raptor.tcl --device 1VG28
  ./build/bin/raptor --batch --compiler dummy --mute --script tests/TestBatch/test_compiler_mt.tcl
  ./build/bin/raptor --batch --compiler dummy --mute --script tests/TestBatch/test_compiler_batch.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/and2_gemini/raptor.tcl 
@@ -198,14 +199,23 @@ else
  ./build/bin/raptor --batch --mute --script tests/Testcases/counter_mixed/raptor.tcl
  ./build/bin/raptor --batch --mute --script tests/TestBatch/oneff_clean/raptor.tcl
  ./build/bin/raptor --batch --mute --script tests/Testcases/rom/raptor.tcl
+endif
+
+# Too large for Github Action
+test/batch_gen3: run-cmake-release
+ifeq ($(RAPTOR_PUB),1)
+else
  cd tests/Testcases/and2_bitstream; ../../../build/bin/raptor --batch --mute --script raptor.tcl
 endif
+
 solver/tests: release
 ifeq ($(RAPTOR_PUB),1)
 else
- ./build/bin/raptor --batch --script tests/Testcases/partitioner_aes_verilog/run_raptor.tcl
+ ./build/bin/raptor --batch --mute --script tests/Testcases/partitioner_aes_verilog/run_raptor.tcl
 endif
 
+test/batch_all: test/batch test/batch_gen2 solver/tests test/batch_gen3
+
 lib-only: run-cmake-release
  cmake --build build --target raptor_gui -j $(CPU_CORES)
 

diff --git a/tests/TestIP/axi2axilite_bridge/v1_0/axi2axilite_bridge.tcl b/tests/TestIP/axi2axilite_bridge/v1_0/axi2axilite_bridge.tcl
@@ -1,6 +1,6 @@
 create_design axi2axilite_bridge_prj
 
-target_device 1GE100-ES1
+target_device 1VG28
 
 #set path here
 

diff --git a/tests/Testcases/and2_2clks/constraints.sdc b/tests/Testcases/and2_2clks/constraints.sdc
@@ -5,4 +5,4 @@ create_clock -period 5 [get_ports {clk1}] -name clk1
 create_clock -period 5 [get_ports {clk2}] -name clk2
 set_clock_groups -group [get_clocks {clk1}] -group [get_clocks {clk2}] -physically_exclusive
 create_clock -name clk3 -period 6
-set_false_path -from [get_clocks {clk1}] -to [get_clocks {clk2}]
+#set_false_path -from [get_clocks {clk1}] -to [get_clocks {clk2}]
diff --git a/tests/Testcases/and2_gemini/raptor.tcl b/tests/Testcases/and2_gemini/raptor.tcl
@@ -6,7 +6,7 @@ add_constraint_file pin_mapping.pin
 add_constraint_file constraints.sdc
 
 # Device target
-target_device 1GE100-ES1
+target_device 1VG28
 #bitstream_config_files -bitstream ""
 # Compilation
 analyze

diff --git a/tests/Testcases/counter_mixed/pin_mapping.pin b/tests/Testcases/counter_mixed/pin_mapping.pin
@@ -1,10 +1,10 @@
 
-set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P
-set_pin_loc reset HP_1_CC_28_14P
+set_property mode Mode_BP_SDR_A_RX HR_3_0_0P
+set_pin_loc reset HR_3_0_0P
 
-set_property mode Mode_RATE_4_A_TX HP_1_24_12P
-set_pin_loc counter[0] HP_1_24_12P f2g_tx_out[0]_A
-set_pin_loc counter[1] HP_1_24_12P f2g_tx_out[1]_A
-set_pin_loc counter[2] HP_1_24_12P f2g_tx_out[2]_A
-set_pin_loc counter[3] HP_1_24_12P f2g_tx_out[3]_A
+set_property mode Mode_RATE_4_A_TX HR_5_0_0P
+set_pin_loc counter[0] HR_5_0_0P f2g_tx_out[0]_A
+set_pin_loc counter[1] HR_5_0_0P f2g_tx_out[1]_A
+set_pin_loc counter[2] HR_5_0_0P f2g_tx_out[2]_A
+set_pin_loc counter[3] HR_5_0_0P f2g_tx_out[3]_A
 
diff --git a/tests/Testcases/counter_vhdl/pin_mapping.pin b/tests/Testcases/counter_vhdl/pin_mapping.pin
@@ -1,10 +1,10 @@
 
-set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P
-set_pin_loc reset HP_1_CC_28_14P
+set_property mode Mode_BP_SDR_A_RX HR_3_0_0P
+set_pin_loc reset HR_3_0_0P
 
-set_property mode Mode_RATE_4_A_TX HP_1_24_12P
-set_pin_loc counter[0] HP_1_24_12P f2g_tx_out[0]_A
-set_pin_loc counter[1] HP_1_24_12P f2g_tx_out[1]_A
-set_pin_loc counter[2] HP_1_24_12P f2g_tx_out[2]_A
-set_pin_loc counter[3] HP_1_24_12P f2g_tx_out[3]_A
+set_property mode Mode_RATE_4_A_TX HR_5_0_0P
+set_pin_loc counter[0] HR_5_0_0P f2g_tx_out[0]_A
+set_pin_loc counter[1] HR_5_0_0P f2g_tx_out[1]_A
+set_pin_loc counter[2] HR_5_0_0P f2g_tx_out[2]_A
+set_pin_loc counter[3] HR_5_0_0P f2g_tx_out[3]_A
 
diff --git a/tests/Testcases/counter_vhdl/raptor.tcl b/tests/Testcases/counter_vhdl/raptor.tcl
@@ -10,7 +10,7 @@ add_simulation_file -VHDL_1993 testbench.vhd
 set_top_testbench tb_counters
 
 # Device target
-target_device 1GE100-ES1
+target_device GEMINI_COMPACT_10x8
 
 # Compilation/Simulation
 analyze

diff --git a/tests/Testcases/ip_gen_axis_conv/raptor.tcl b/tests/Testcases/ip_gen_axis_conv/raptor.tcl
@@ -1,5 +1,5 @@
 create_design ip_test
-target_device 1GE75
+target_device 1VG28
 configure_ip axis_width_converter_v1_0 -mod_name conv32_16 -version 1.0 -Pcore_in_width=32 -Pcore_out_width=16 -Pcore_reverse=0 -out_file rs_ips/conv32_16.v
 ipgenerate
 set_top_module use_ip

diff --git a/tests/Testcases/oneff/pin_mapping.pin b/tests/Testcases/oneff/pin_mapping.pin
@@ -1,9 +1,9 @@
-set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P
-set_pin_loc d HP_1_CC_28_14P
+set_property mode Mode_BP_SDR_A_RX HR_3_0_0P
+set_pin_loc d HR_3_0_0P
 
-set_property mode Mode_BP_SDR_A_RX HP_1_26_13P
-set_pin_loc rstn HP_1_26_13P
+set_property mode Mode_BP_SDR_A_RX HR_2_0_0P
+set_pin_loc rstn HR_2_0_0P
 
-set_property mode Mode_BP_SDR_A_TX HP_1_24_12P
-set_pin_loc q HP_1_24_12P
+set_property mode Mode_BP_SDR_A_TX HR_5_0_0P
+set_pin_loc q HR_5_0_0P
 
diff --git a/tests/Testcases/oneff/raptor.tcl b/tests/Testcases/oneff/raptor.tcl
@@ -11,7 +11,7 @@ add_simulation_file sim_main.cpp
 set_top_testbench syn_tb
 
 # Device target
-target_device 1GE75
+target_device GEMINI_COMPACT_10x8
 
 # Compilation/Simulation
 analyze

diff --git a/tests/Testcases/partitioner_aes_verilog/run_raptor.tcl b/tests/Testcases/partitioner_aes_verilog/run_raptor.tcl
@@ -21,7 +21,7 @@ set project_name AES_DECRYPT_partitioner
 
 puts "Creating $project_name..."
 create_design $project_name
-target_device 1GE100-ES1
+target_device 1VG28
 add_design_file Src/aes_decrypt128.sv Src/aes_decrypt256.sv Src/gfmul.sv Src/InvMixCol_slice.sv Src/InvSbox.sv Src/InvSubBytes.sv Src/KeyExpand192.sv Src/KschBuffer.sv Src/Sbox.sv Src/aes_decrypt192.sv Src/decrypt.sv Src/InvAddRoundKey.sv Src/InvMixColumns.sv Src/InvShiftRows.sv Src/KeyExpand128.sv Src/KeyExpand256.sv Src/RotWord.sv Src/SubWord.sv -SV_2012
 add_design_file Src/MUXF7.v Src/MUXF8.v Src/decrypt_top.v
 add_constraint_file constraints.sdc

diff --git a/tests/Testcases/rom/raptor.tcl b/tests/Testcases/rom/raptor.tcl
@@ -4,7 +4,7 @@ add_design_file top.v
 set_top_module SBox
 
 # Device target
-target_device 1GE100-ES1
+target_device 1VG28
 # Compilation
 analyze
 synthesize delay

diff --git a/tests/Testcases/sasc_testcase/raptor.tcl b/tests/Testcases/sasc_testcase/raptor.tcl
@@ -1,6 +1,6 @@
 create_design sasc
 # Device setup
-target_device 1GE75
+target_device 1VG28
 # Design setup
 add_design_file -V_2001 ./rtl/timescale.v ./rtl/sasc_brg.v ./rtl/sasc_fifo4.v ./rtl/sasc.v
 set_top_module sasc

diff --git a/tests/Testcases/vex_soc/raptor_vex_no_carry.tcl b/tests/Testcases/vex_soc/raptor_vex_no_carry.tcl
@@ -1,6 +1,5 @@
 create_design vex_soc_no_carry
 target_device GEMINI_COMPACT_62x44
-add_include_path ./
 add_library_path rtl/
 add_library_ext .v .sv
 add_design_file rtl/vex_soc.v

diff --git a/tests/tcl_examples/aes_decrypt_gate/raptor_cmd.tcl b/tests/tcl_examples/aes_decrypt_gate/raptor_cmd.tcl
@@ -0,0 +1,25 @@
+# /*******************************************************************************
+# Copyright (c) 2022-2024 Rapid Silicon
+# This source code contains proprietary information belonging to Rapid Silicon
+# (the "licensor") released under license and non-disclosure agreement to the
+# recipient (the "licensee").
+# The information shared and protected by the license and non-disclosure agreement
+# includes but is not limited to the following:
+# * operational algorithms of the product
+# * logos, graphics, source code, and visual presentation of the product
+# * confidential operational information of the licensor
+# The recipient of this source code is NOT permitted to publicly disclose,
+# re-use, archive beyond the period of the license agreement, transfer to a
+# sub-licensee, or re-implement any portion of the content covered by the license
+# and non-disclosure agreement without the prior written consent of the licensor.
+# *********************************************************************************/
+# Version : 2024.02
+# Build : 1.0.0
+# Hash : 28a24fb
+# Date : Feb 23 2024
+# Type : Engineering
+# Log Time : Sun Feb 25 05:15:29 2024 GMT
+source /home/alain/Neulink-Semi/Raptor/build/share/raptor/etc/init/flow.tcl
+gui_start
+gui_stop; exit
+gui_stop
diff --git a/tests/tcl_examples/aes_decrypt_verilog/run_raptor.tcl b/tests/tcl_examples/aes_decrypt_verilog/run_raptor.tcl
@@ -10,7 +10,7 @@ set project_name AES_DECRYPT_VERILOG
 
 puts "Creating $project_name..."
 create_design $project_name
-target_device 1GE75
+target_device 1VG28
 add_design_file Src/aes_decrypt128.sv Src/aes_decrypt256.sv Src/gfmul.sv Src/InvMixCol_slice.sv Src/InvSbox.sv Src/InvSubBytes.sv Src/KeyExpand192.sv Src/KschBuffer.sv Src/Sbox.sv Src/aes_decrypt192.sv Src/decrypt.sv Src/InvAddRoundKey.sv Src/InvMixColumns.sv Src/InvShiftRows.sv Src/KeyExpand128.sv Src/KeyExpand256.sv Src/RotWord.sv Src/SubWord.sv -SV_2012
 add_design_file Src/MUXF7.v Src/MUXF8.v Src/decrypt_top.v
 add_constraint_file constraints.sdc

diff --git a/tests/tcl_examples/and2_verilog/constraints.sdc b/tests/tcl_examples/and2_verilog/constraints.sdc
@@ -1,9 +1,9 @@
 # SDC file example
 
 # Setting a clock frequency of 200 MHz (5nS period)
-create_clock -period 5 clk
-set_input_delay -max 0 -clock clk [get_ports {a}] 
-set_input_delay -max 0 -clock clk [get_ports {b}]
-set_input_delay -max 0 -clock clk [get_ports {reset}]
-set_output_delay -max 0 -clock clk [get_ports {c}]
+#create_clock -period 5 clk
+#set_input_delay -max 0 -clock clk [get_ports {a}] 
+#set_input_delay -max 0 -clock clk [get_ports {b}]
+#set_input_delay -max 0 -clock clk [get_ports {reset}]
+#set_output_delay -max 0 -clock clk [get_ports {c}]
 
diff --git a/tests/tcl_examples/and2_verilog/run_raptor.tcl b/tests/tcl_examples/and2_verilog/run_raptor.tcl
@@ -18,7 +18,7 @@ add_constraint_file constraints.sdc
 add_simulation_file ./Src/testbench_and2.v
 set_top_testbench testbench_and2
 # Device target
-target_device 1GE75
+target_device 1VG28
 
 # RTL Simulation
 simulate rtl icarus

diff --git a/tests/tcl_examples/counter_verilog/run_raptor.tcl b/tests/tcl_examples/counter_verilog/run_raptor.tcl
@@ -15,7 +15,7 @@ add_design_file Src/counter.v
 set_top_module counter
 add_constraint_file constraints.sdc
 # Device target
-target_device 1GE75
+target_device 1VG28
 
 # Compilation
 puts "Compiling $project_name..."

diff --git a/tests/tcl_examples/counter_vhdl/run_raptor.tcl b/tests/tcl_examples/counter_vhdl/run_raptor.tcl
@@ -17,7 +17,7 @@ add_constraint_file constraints.sdc
 add_simulation_file -VHDL_1993 Src/testbench.vhd
 set_top_testbench tb_counters
 # Device target
-target_device 1GE75
+target_device 1VG28
 
 # Compilation/Simulation
 puts "Compiling $project_name..."

diff --git a/tests/tcl_examples/ip_gen_axis_conv/run_raptor.tcl b/tests/tcl_examples/ip_gen_axis_conv/run_raptor.tcl
@@ -10,7 +10,7 @@ set project_name ip_test
 
 puts "Creating $project_name..."
 create_design $project_name
-target_device 1GE75
+target_device 1VG28
 add_design_file Src/use_ip.v
 add_constraint_file constraints.sdc
 set_top_module use_ip

diff --git a/tests/tcl_examples/oneff_verilog/constraints.sdc b/tests/tcl_examples/oneff_verilog/constraints.sdc
@@ -1,5 +1,5 @@
 # -name is used for creating virtual clock and for actual clock -name option will not be used
-create_clock -period 2.5 clock0
-set_input_delay 1 -clock clock0 [get_ports {d}]
-set_input_delay 1 -clock clock0 [get_ports {rstn}]
-set_output_delay 1 -clock clock0 [get_ports {q}]
+#create_clock -period 2.5 clock0
+#set_input_delay 1 -clock clock0 [get_ports {d}]
+#set_input_delay 1 -clock clock0 [get_ports {rstn}]
+#set_output_delay 1 -clock clock0 [get_ports {q}]
diff --git a/tests/tcl_examples/oneff_verilog/pin_mapping.pin b/tests/tcl_examples/oneff_verilog/pin_mapping.pin
@@ -1,9 +1,9 @@
-set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P
-set_pin_loc d HP_1_CC_28_14P
+#set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P
+#set_pin_loc d HP_1_CC_28_14P
 
-set_property mode Mode_BP_SDR_A_RX HP_1_26_13P
-set_pin_loc rstn HP_1_26_13P
+#set_property mode Mode_BP_SDR_A_RX HP_1_26_13P
+#set_pin_loc rstn HP_1_26_13P
 
-set_property mode Mode_BP_SDR_A_TX HP_1_24_12P
-set_pin_loc q HP_1_24_12P
+#set_property mode Mode_BP_SDR_A_TX HP_1_24_12P
+#set_pin_loc q HP_1_24_12P
 
diff --git a/tests/tcl_examples/oneff_verilog/run_raptor.tcl b/tests/tcl_examples/oneff_verilog/run_raptor.tcl
@@ -11,7 +11,7 @@ add_simulation_file sim_main.cpp
 set_top_testbench syn_tb
 
 # Device target
-target_device 1GE75
+target_device 1VG28
 
 # Compilation/Simulation
 analyze
@@ -22,6 +22,7 @@ simulation_options verilator compilation rtl ""
 simulate rtl verilator syn_tb_rtl.fst
 
 # Synthesis
+synth_options -inferred_io
 synthesize delay
 
 # clean default flags for wrapper

diff --git a/tests/tcl_examples/sasc_testcase/run_raptor.tcl b/tests/tcl_examples/sasc_testcase/run_raptor.tcl
@@ -12,7 +12,7 @@ puts "Creating $project_name..."
 # Create Project
 create_design $project_name
 # Device setup
-target_device 1GE75
+target_device 1VG28
 # Design setup
 add_design_file ./Src/timescale.v ./Src/sasc_brg.v ./Src/sasc_fifo4.v ./Src/sasc.v
 add_constraint_file constraints.sdc