Enable IO inference (#1565)

CMakeLists.txt

@@ -200,7 +200,7 @@ add_subdirectory(IP_Catalog)
 # Raptor version
 set(VERSION_MAJOR 1)
 set(VERSION_MINOR 0)
-set(VERSION_PATCH 6)
+set(VERSION_PATCH 7)
 
 execute_process(COMMAND git config --global --add safe.directory ${CMAKE_CURRENT_SOURCE_DIR}
  COMMAND git rev-parse --short HEAD

tests/Testcases/and2_verilog/run_raptor.tcl

@@ -36,10 +36,10 @@ simulate rtl icarus
 
 # Compilation
 puts "Compiling $project_name..."
-parser_type surelog
+
 analyze
 #synth_options -inferred_io
-#parser_type surelog
+
 synthesize delay
 simulate gate icarus
 #pnr_options --read_vpr_constraints and2_part.xml
@@ -48,7 +48,7 @@ place
 route
 sta
 power
-bitstream 
 simulate pnr icarus
+bitstream 
 
 puts "Completed $project_name...\n"

tests/Testcases/and2_wio/constraints.sdc

@@ -1,9 +1,9 @@
 # SDC file example
 
 # Setting a clock frequency of 200 MHz (5nS period)
-#create_clock -period 5 clk
-#set_input_delay -max 0 -clock clk [get_ports {a}] 
-#set_input_delay -max 0 -clock clk [get_ports {b}]
-#set_input_delay -max 0 -clock clk [get_ports {reset}]
-#set_output_delay -max 0 -clock clk [get_ports {c}]
+create_clock -period 5 clk
+set_input_delay -max 0 -clock clk [get_ports {a}] 
+set_input_delay -max 0 -clock clk [get_ports {b}]
+set_input_delay -max 0 -clock clk [get_ports {reset}]
+set_output_delay -max 0 -clock clk [get_ports {c}]
 

tests/Testcases/oneff_wio/constraints.sdc

@@ -1,5 +1,5 @@
 # -name is used for creating virtual clock and for actual clock -name option will not be used
-#create_clock -period 2.5 clock0
-#set_input_delay 1 -clock clock0 [get_ports {d}]
-#set_input_delay 1 -clock clock0 [get_ports {rstn}]
-#set_output_delay 1 -clock clock0 [get_ports {q}]
+create_clock -period 2.5 clock0
+set_input_delay 1 -clock clock0 [get_ports {d}]
+set_input_delay 1 -clock clock0 [get_ports {rstn}]
+set_output_delay 1 -clock clock0 [get_ports {q}]