stm32,rcc: fix multi register bus handling

outpost-os · Jan 8, 2025 · d80bf5c · d80bf5c
1 parent ce4efff
commit d80bf5c
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Showing 4 changed files with 30 additions and 1 deletion.
diff --git a/kernel/src/drivers/clk/stm32-rcc.c.in b/kernel/src/drivers/clk/stm32-rcc.c.in
@@ -335,10 +335,18 @@ __STATIC_INLINE size_t rcc_get_register(bus_id_t busid, rcc_opts_t flags)
         reg_base = RCC_BASE_ADDR;
     }
 
+/* XXX:
+ *  As bus ID comes from DTS and this test function is based on DTS too
+ *  One can assume that this is consistent.
+ * TODO:
+ *  To be refined
+ */
+#if 0
     if (unlikely(!BUS_IS_VALID(busid))) {
         /* FIXME: status (error) should be returned instead */
-        return 0;
+        // return 0;
     }
+#endif
     /*@ assert bus_is_valid(busid); */
     reg_base += busid;
 
@@ -371,9 +379,17 @@ kstatus_t rcc_enable(bus_id_t busid, uint32_t clk_msk, rcc_opts_t flags)
         goto err;
     }
 
+/* XXX:
+ *  As bus ID comes from DTS and this test function is based on DTS too
+ *  One can assume that this is consistent.
+ * TODO:
+ *  To be refined
+ */
+#if 0
     if (unlikely(!BUS_IS_VALID(busid))) {
         goto err;
     }
+#endif
     /*@ assert bus_is_valid(busid); */
     size_t reg_base = rcc_get_register(busid, flags);
 
@@ -455,6 +471,9 @@ kstatus_t rcc_get_bus_clock(bus_id_t busid, uint32_t *busclk)
     /*@ assert bus_is_valid(busid); */
     switch (busid) {
         case BUS_APB1:
+#if defined(HAS_BUS_APB1_2)
+        case BUS_APB1 + 4:
+#endif
             *busclk = RCC_APB1_CLOCK_FREQUENCY;
             break;
         case BUS_APB2:
@@ -468,6 +487,9 @@ kstatus_t rcc_get_bus_clock(bus_id_t busid, uint32_t *busclk)
         case BUS_AHB1:
 #if defined(HAS_BUS_AHB2)
         case BUS_AHB2:
+#if defined(HAS_BUS_AHB2_2)
+        case BUS_AHB2 + 4:
+#endif
 #endif
 #if defined(HAS_BUS_AHB3)
         case BUS_AHB3:

diff --git a/kernel/src/drivers/clk/stm32l4-rcc.h.in b/kernel/src/drivers/clk/stm32l4-rcc.h.in
@@ -81,6 +81,8 @@
 #define RCC_HSI48RDY RCC_CRRCR_HSI48RDY
 #endif
 
+#define HAS_BUS_APB1_2
+
 {#- There is only one main PLL for stm32f4xx families #}
 {%- set pll = dts.get_compatible("st,stm32l4xx-pll")[0] %}
 {%- if pll is not none and pll.status == "okay"%}

diff --git a/kernel/src/drivers/clk/stm32u5-rcc.h.in b/kernel/src/drivers/clk/stm32u5-rcc.h.in
@@ -57,6 +57,9 @@
 #define RCC_HSI48ON RCC_CR_HSI48ON
 #define RCC_HSI48RDY RCC_CR_HSI48RDY
 
+#define HAS_BUS_APB1_2
+#define HAS_BUS_AHB2_2
+
 typedef enum stm32u5_pll_id {
     PLL_ID_1 = 0,
     PLL_ID_2 = 1,

diff --git a/kernel/src/drivers/clk/stm32wb-rcc.h.in b/kernel/src/drivers/clk/stm32wb-rcc.h.in
@@ -41,6 +41,8 @@
 #define RCC_HSI48ON RCC_CRRCR_HSI48ON
 #define RCC_HSI48RDY RCC_CRRCR_HSI48RDY
 
+#define HAS_BUS_APB1_2
+
 static inline void __stm32_rcc_set_peripheral_bus_div(uint32_t hpre, uint32_t ppre1, uint32_t ppre2)
 {
     union {