kernel,driver,busses: enhanced stm32 busses detection in template #111
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Handle more complex bus architecture. Some SOC have got more busses than available registers and reset and clocken might not be consistent. e.g. AHB3/4 on the same xxxENR register and APB3ENR reserved for companion core.
pthierry-ledger
approved these changes
Jan 8, 2025
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Handle more complex bus architecture.
Some SOC have got more busses than available registers and reset and clocken might not be consistent.
e.g. AHB3/4 on the same xxxENR register and APB3ENR reserved for companion core.