This is the first proper release of sv2chisel, the automated (System)Verilog to Chisel translator.
> Overview of features and limitations < including most notably:
- sv2chisel translation options
- sv2chisel-helpers introducing Chisel as IP integration utilities
The root README file provides all instructions to get started (spoiler: it's quite easy)
Feel free to report any issue, all contributions are welcome!
Versioning is aligned on chisel stack version policy and this release is fully compatible with chisel stack x.5.+:
- sv2chisel generates valid chisel3 3.5.+
- sv2chisel-helpers is published with a dependency on chisel3 3.5.0, de facto compatible with all chisel3 3.5.+ versions
Downloads available below, provided with GPG signatures and with the following flavors:
- Native standalone binaries for linux, mac and windows.
- Cross platform fat jar with launcher in tarball (requiring an existing java 8+ installation)
To check the signature, download both the executable and its signature in the same folder and run for example on linux gpg --verify sv2chisel_linux_amd64.asc
sv2chisel and sv2chisel-helpers are also available directly from maven central