Proof of concept periph 0 UART

hdl/ip/vhd/espi/espi_spec_regs.rdl

@@ -100,7 +100,7 @@ addrmap eSPI_Spec {
         field {
             desc = "OOB Message Channel Supported";
             sw = r;
-        } oob_support[2:2] = 0x1;
+        } oob_support[2:2] = 0x0;
         field {
             desc = "Virtual Wire Channel Supported";
             sw = r;

hdl/ip/vhd/espi/espi_target_top.vhd

@@ -220,7 +220,6 @@ begin
        clk => clk,
        reset => reset,
        axi_if => axi_if,
-       msg_en => msg_en,
        dbg_chan => dbg_chan
    );
 

hdl/ip/vhd/espi/link_layer/link_layer_pkg.vhd

@@ -147,6 +147,9 @@ package body link_layer_pkg is
                     when message_with_data =>
                         -- opcode, standard header (3), 5 mesg header bytes, length bytes, crc
                         return To_StdLogicVector(1 + 3 + 5 + to_integer(h.len) + 1, 13);
+                    when mem_write_32 =>
+                        -- opcode, standard header (3), 4 addr bytes, length bytes, crc
+                        return To_StdLogicVector(1 + 3 + 4 + to_integer(h.len) + 1, 13);
                     when others =>
                         assert false report "Unsupported cycle type" severity failure;
                         return To_StdLogicVector(0, 13);

hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd

@@ -82,9 +82,9 @@ begin
     np_free <= '0';
     np_avail <= '0';
     pc_free <= '1' when (fifo_depth - rx_wusedwds) >= max_msg_size else '0';
-    pc_avail <= (not tx_rempty) and pc_avail_not_masked and msg_not_oob_syncd;
-    oob_free <= '1' when (fifo_depth - rx_wusedwds) >= max_msg_size else '0';
-    oob_avail <= (not tx_rempty) and pc_avail_not_masked and (not msg_not_oob_syncd);
+    pc_avail <= '0'; --(not tx_rempty) and pc_avail_not_masked and msg_not_oob_syncd;
+    oob_free <= '0'; --'1' when (fifo_depth - rx_wusedwds) >= max_msg_size else '0';
+    oob_avail <= '0'; --(not tx_rempty) and pc_avail_not_masked and (not msg_not_oob_syncd);
 
     host_to_sp_espi.ready <= not rx_wfull;
     -- tx_rusedwds is potentailly cycles behind the empty flag due to fifo latencies.
@@ -95,6 +95,8 @@ begin
 
     fifo_read_by_espi <= sp_to_host_espi.st.valid and sp_to_host_espi.st.ready;
 
+    -- Need a bit of a re-write here.
+
     -- We want to hold some data to let the bytes accumulate
     -- so that we're not doing multiple transactions (which are multi-byte)
     -- but just transferring 1-2 bytes at a time.

hdl/ip/vhd/espi/sys_regs/espi_regs.rdl

@@ -23,9 +23,6 @@ addrmap espi_regs {
     reg {
         name = "Control Register";
         desc = "";
-        field {
-            desc = "Respond back on periph 0 channel vs oob";
-        } msg_en[4:4] =  0;
         field {
             desc = "Set to one to reset the command FIFO. Cleared by hardware after reset.";
         } cmd_fifo_reset[3:3] =  0;

hdl/ip/vhd/espi/sys_regs/espi_regs.vhd

@@ -20,7 +20,6 @@ entity espi_regs is
         reset : in    std_logic;
         -- axi interface
         axi_if : view axil_target;
-        msg_en : out std_logic;
         -- debug interface
         dbg_chan : view dbg_regs_if
 
@@ -49,7 +48,6 @@ begin
     fifo_status_reg.resp_used_wds <= dbg_chan.rdstatus.usedwds;
     status_reg.busy <= dbg_chan.busy;
     flags_reg.alert <= dbg_chan.alert_pending;
-    msg_en <= control_reg.msg_en;
 
     -- unpack the record
     axi_if.write_response.resp  <= OKAY;

hdl/ip/vhd/espi/txn_layer/command_processor.vhd

@@ -138,7 +138,12 @@ architecture rtl of command_processor is
                         next_state.next_state := parse_msg_header;
                         next_state.cmd_addr_bytes := 0;
                         next_state.cmd_payload_bytes := to_integer(header.length);
+                    when mem_write_32 =>
+                        -- mem writes have a payload of "length"
+                        next_state.next_state := parse_addr_header;
+                        next_state.cmd_payload_bytes := to_integer(header.length);
                     when others =>
+                        -- use the default value for next_state
                         null;
                 end case;
             when opcode_put_oob =>
@@ -163,7 +168,9 @@ begin
     vwire_if.wstrobe <= r.vwire_wstrobe;
 
     host_to_sp_espi.data <= data_from_host.data;
-    host_to_sp_espi.valid <= data_from_host.valid when r.cmd_header.opcode.value = opcode_put_pc and r.cmd_header.cycle_kind = message_with_data and r.state = parse_data else 
+    host_to_sp_espi.valid <= data_from_host.valid when r.cmd_header.opcode.value = opcode_put_pc and 
+                                                        (r.cmd_header.cycle_kind = message_with_data  or
+                                                         r.cmd_header.cycle_kind = mem_write_32) and r.state = parse_data else 
                              data_from_host.valid when r.cmd_header.opcode.value = opcode_put_oob and r.state = parse_data else '0';
     -- pass through the flash channel requests here
     flash_req.espi_hdr             <= r.cmd_header;

hdl/ip/vhd/espi/txn_layer/espi_protocol_pkg.vhd

@@ -42,6 +42,8 @@ package espi_protocol_pkg is
     -- eSPI Channel
     constant mem_read_32 : std_logic_vector(7 downto 0) := "00000000";
     constant mem_read_64 : std_logic_vector(7 downto 0) := "00000010";
+    constant mem_write_32 : std_logic_vector(7 downto 0) := "00000001";
+    constant mem_write_64 : std_logic_vector(7 downto 0) := "00000011";
     -- Flash channel (from  server addendum)
     constant flash_read : std_logic_vector(7 downto 0)      := "00000000";
     constant success_no_data : std_logic_vector(7 downto 0) := "00000110";