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Rebased from upstream
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mbudiu-vmw committed Mar 29, 2017
1 parent 71fa5f1 commit 5910398
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Showing 6 changed files with 128 additions and 1 deletion.
2 changes: 1 addition & 1 deletion midend/midEndLast.h
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ namespace P4 {
class MidEndLast : public Inspector {
public:
MidEndLast() { setName("MidEndLast"); }
bool preorder(const IR::P4Program* program) override
bool preorder(const IR::P4Program*) override
{ return false; }
};

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3 changes: 3 additions & 0 deletions testdata/p4_16_samples_outputs/interface-midend.p4
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,9 @@ extern Crc16<T> {
}

control p() {
@name("crc0") Crc16<bit<32>>() crc0;
@name("crc1") Crc16<int<32>>(32s0) crc1;
@name("crc2") Crc16<int<32>>() crc2;
apply {
}
}
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2 changes: 2 additions & 0 deletions testdata/p4_16_samples_outputs/interface1-midend.p4
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@ extern Y {
}

parser p() {
@name("x") X<int<32>>() x;
@name("y") Y() y;
state start {
transition accept;
}
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60 changes: 60 additions & 0 deletions testdata/p4_16_samples_outputs/issue364-bmv2-midend.p4
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@@ -0,0 +1,60 @@
#include <core.p4>
#include <v1model.p4>

header hdr {
bit<32> a;
}

struct Headers {
hdr h;
}

struct Meta {
}

parser p(packet_in b, out Headers h, inout Meta m, inout standard_metadata_t sm) {
state start {
b.extract<hdr>(h.h);
transition accept;
}
}

control vrfy(in Headers h, inout Meta m) {
apply {
}
}

control update(inout Headers h, inout Meta m) {
apply {
}
}

control egress(inout Headers h, inout Meta m, inout standard_metadata_t sm) {
apply {
}
}

control deparser(packet_out b, in Headers h) {
apply {
b.emit<hdr>(h.h);
}
}

control ingress(inout Headers h, inout Meta m, inout standard_metadata_t sm) {
@name("c") direct_counter(CounterType.packets) c;
@name("my_action") action my_action_0(bit<32> a) {
sm.egress_spec = (bit<9>)a;
}
@name("t") table t {
actions = {
my_action_0();
}
const default_action = my_action_0(32w0);
counters = c;
}
apply {
t.apply();
}
}

V1Switch<Headers, Meta>(p(), vrfy(), ingress(), egress(), update(), deparser()) main;
1 change: 1 addition & 0 deletions testdata/p4_16_samples_outputs/spec-ex16-midend.p4
Original file line number Diff line number Diff line change
Expand Up @@ -15,3 +15,4 @@ control Map1(in bit<32> d) {
}

Switch<bit<32>>(P(), Map1()) main;
Switch<bit<32>>(P(), Map1()) main1;
61 changes: 61 additions & 0 deletions testdata/p4_16_samples_outputs/unused-counter-bmv2-midend.p4
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@@ -0,0 +1,61 @@
#include <core.p4>
#include <v1model.p4>

header hdr {
bit<32> a;
}

struct Headers {
hdr h;
}

struct Meta {
}

parser p(packet_in b, out Headers h, inout Meta m, inout standard_metadata_t sm) {
state start {
b.extract<hdr>(h.h);
transition accept;
}
}

control vrfy(in Headers h, inout Meta m) {
apply {
}
}

control update(inout Headers h, inout Meta m) {
apply {
}
}

control egress(inout Headers h, inout Meta m, inout standard_metadata_t sm) {
apply {
}
}

control deparser(packet_out b, in Headers h) {
apply {
b.emit<hdr>(h.h);
}
}

control ingress(inout Headers h, inout Meta m, inout standard_metadata_t sm) {
@name("c") direct_counter(CounterType.packets) c;
@name("c1") direct_counter(CounterType.packets) c1;
@name("my_action") action my_action_0(bit<32> a) {
sm.egress_spec = (bit<9>)a;
}
@name("t") table t {
actions = {
my_action_0();
}
const default_action = my_action_0(32w0);
counters = c;
}
apply {
t.apply();
}
}

V1Switch<Headers, Meta>(p(), vrfy(), ingress(), egress(), update(), deparser()) main;

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