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  • Saint-Petersburg, Russia

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  1. basic_verilog Public

    Must-have verilog systemverilog modules

    Verilog 1.8k 407

  2. vivado_design_space_explorer_template Public

    Iterative compilation and reporting scripts for AMD / Xilinx Vivado

    SystemVerilog 9 2

  3. xilinx_max_power Public

    Stress test power subsystem of your Xilinx FPGA board

    SystemVerilog 5 1

  4. quartus_design_space_explorer_template Public

    Iterative compilation and reporting scripts for Intel / Altera Quartus

    Makefile 6 1

  5. avr_assembler_macros Public

    Collection of assembler macros for Atmel AVR microcontroller

    3 1

  6. altium_designer_settings_and_preferences Public

    Templates, settings and preferences to use with Altium Designer

    4 5

26 contributions in the last year

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Activity overview

Loading A graph representing pConst's contributions from July 21, 2024 to July 24, 2025. The contributions are 56% commits, 44% pull requests, 0% issues, 0% code review.   Code review   Issues 44% Pull requests 56% Commits

Contribution activity

July 2025

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