Undo openhwgroup#721 and openhwgroup#723 fix from PR openhwgroup#824.

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo · Aug 29, 2023 · 8330d1e · 8330d1e
1 parent c36466b
commit 8330d1e
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Showing 2 changed files with 9 additions and 18 deletions.
diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv
@@ -901,8 +901,6 @@ module cv32e40p_core
       .data_misaligned_ex_i(data_misaligned_ex),  // from ID/EX pipeline
       .data_misaligned_o   (data_misaligned),
 
-      .apu_busy_i(apu_busy),
-
       .p_elw_start_o (p_elw_start),
       .p_elw_finish_o(p_elw_finish),
 

diff --git a/rtl/cv32e40p_load_store_unit.sv b/rtl/cv32e40p_load_store_unit.sv
@@ -59,8 +59,6 @@ module cv32e40p_load_store_unit #(
     input  logic data_misaligned_ex_i,  // misaligned access in last ld/st   -> from ID/EX pipeline
     output logic data_misaligned_o,  // misaligned access was detected    -> to controller
 
-    input logic apu_busy_i,
-
     input  logic [5:0] data_atop_ex_i,  // atomic instructions signal        -> from ex stage
     output logic [5:0] data_atop_o,  // atomic instruction signal         -> core output
 
@@ -76,8 +74,6 @@ module cv32e40p_load_store_unit #(
 
   localparam DEPTH = 2;  // Maximum number of outstanding transactions
 
-  logic data_req_ex_filtered;  // data request from ex stage filtered when it is misaligned and there is an on-going APU instruction
-
   // Transaction request (to cv32e40p_obi_interface)
   logic trans_valid;
   logic trans_ready;
@@ -352,14 +348,12 @@ module cv32e40p_load_store_unit #(
   // Busy if there are ongoing (or potentially outstanding) transfers
   assign busy_o = (cnt_q != 2'b00) || trans_valid;
 
-  assign data_req_ex_filtered = data_req_ex_i & !(apu_busy_i & (data_misaligned_o | data_misaligned_ex_i));
-
   //////////////////////////////////////////////////////////////////////////////
   // Transaction request generation
   //
   // Assumes that corresponding response is at least 1 cycle after request
   //
-  // - Only request transaction when EX stage requires data transfer (data_req_ex_filtered), and
+  // - Only request transaction when EX stage requires data transfer (data_req_ex_i), and
   // - maximum number of outstanding transactions will not be exceeded (cnt_q < DEPTH)
   //////////////////////////////////////////////////////////////////////////////
 
@@ -376,12 +370,12 @@ module cv32e40p_load_store_unit #(
       // OBI compatible (avoids combinatorial path from data_rvalid_i to data_req_o).
       // Multiple trans_* transactions can be issued (and accepted) before a response
       // (resp_*) is received.
-      assign trans_valid = data_req_ex_filtered && (cnt_q < DEPTH);
+      assign trans_valid = data_req_ex_i && (cnt_q < DEPTH);
     end else begin : gen_pulp_obi
       // Legacy PULP OBI behavior, i.e. only issue subsequent transaction if preceding transfer
       // is about to finish (re-introducing timing critical path from data_rvalid_i to data_req_o)
-      assign trans_valid = (cnt_q == 2'b00) ? data_req_ex_filtered && (cnt_q < DEPTH) :
-                                              data_req_ex_filtered && (cnt_q < DEPTH) && resp_valid;
+      assign trans_valid = (cnt_q == 2'b00) ? data_req_ex_i && (cnt_q < DEPTH) :
+                                              data_req_ex_i && (cnt_q < DEPTH) && resp_valid;
     end
   endgenerate
 
@@ -391,7 +385,7 @@ module cv32e40p_load_store_unit #(
 
   // LSU EX stage readyness requires two criteria to be met:
   // 
-  // - A data request (data_req_ex_filtered) has been forwarded/accepted (trans_valid && trans_ready)
+  // - A data request (data_req_ex_i) has been forwarded/accepted (trans_valid && trans_ready)
   // - The LSU WB stage is available such that EX and WB can be updated in lock step
   //
   // Default (if there is not even a data request) LSU EX is signaled to be ready, else
@@ -400,11 +394,10 @@ module cv32e40p_load_store_unit #(
   // in case there is already at least one outstanding transaction (so WB is full) the EX 
   // and WB stage can only signal readiness in lock step (so resp_valid is used as well).
 
-  assign lsu_ready_ex_o = !(apu_busy_i & (data_misaligned_o | data_misaligned_ex_i)) &
-                          ((data_req_ex_i == 1'b0) ? 1'b1 :
-                           (cnt_q == 2'b00) ? (              trans_valid && trans_ready) : 
-                           (cnt_q == 2'b01) ? (resp_valid && trans_valid && trans_ready) : 
-                                               resp_valid);
+  assign lsu_ready_ex_o = (data_req_ex_i == 1'b0) ? 1'b1 :
+                          (cnt_q == 2'b00) ? (              trans_valid && trans_ready) : 
+                          (cnt_q == 2'b01) ? (resp_valid && trans_valid && trans_ready) : 
+                                              resp_valid;
 
   // Update signals for EX/WB registers (when EX has valid data itself and is ready for next)
   assign ctrl_update = lsu_ready_ex_o && data_req_ex_i;