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Simple ethernet receiver implemented in SystemVerilog

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HDL Ethernet Receiver

Simple ethernet receiver implemented in SystemVerilog: design specification.

Setup

  1. Install Miniconda (reference)

    mkdir -p ~/miniconda3
    wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh -O ~/miniconda3/miniconda.sh
    bash ~/miniconda3/miniconda.sh -b -u -p ~/miniconda3
    rm -rf ~/miniconda3/miniconda.sh
    ~/miniconda3/bin/conda init tcsh
  2. Create environment and install conda dependencies in it

    conda create --name cocotb --channel conda-forge --yes cocotb
  3. Activate environment and install pip dependencies in it

    conda activate cocotb
    pip install -r requirements.txt

Run

The test script is test_recv.py. To view the available arguments, run with the -h/--help argument:

python test_recv.py -h

Clean

cocotb-clean -r

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Simple ethernet receiver implemented in SystemVerilog

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