target/riscv: Don't start user-mode with VILL

This is still under discussion in the psABI, but it's looking like we're
going to forbid VILL in userspace in order to maintain compatibility
with binaries that don't expect implementations to trap whole register
moves under VILL (as in QEMU before 4eff52c ("target/riscv: Add vill
check for whole vector register move instructions"), for example).

Fixes: f8c1f36 ("target/riscv: Set vtype.vill on CPU reset")
Link: riscv-non-isa/riscv-elf-psabi-doc#454
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

target/riscv/cpu.c

@@ -1022,7 +1022,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+#ifdef CONFIG_USER_ONLY
+    env->vill = false;
+#else
     env->vill = true;
+#endif
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.debug) {