internal/lz4block: arm64 decoder improvements

Use fast loop after dict copy. Checking for its possibility costs as
many instructions as jumping over it.

Move SUBS close to conditional branches for CPUs that fuse these
instructions.

Shave one instruction off the remainder handling code after this loop.
A load from register base+register offset has the same latency and
throughput as a load from register+constant offset, at least on
Cortex-A72.

internal/lz4block/decode_arm64.s

@@ -174,11 +174,9 @@ copyDict:
 	CBZ len, copyMatchDone
 
 	// If the match extends beyond the dictionary, the rest is at dstorig.
+	// Recompute the offset for the next check.
 	MOVD dstorig, match
-
-	// The code up to copyMatchLoop1 assumes len >= minMatch.
-	CMP $const_minMatch, len
-	BLO copyMatchLoop1
+	SUB  dstorig, dst, offset
 
 copyMatchTry8:
 	// Copy doublewords if both len and offset are at least eight.
@@ -190,23 +188,22 @@ copyMatchTry8:
 	AND    $7, len, lenRem
 	SUB    $8, len
 copyMatchLoop8:
-	SUBS   $8, len
 	MOVD.P 8(match), tmp1
 	MOVD.P tmp1, 8(dst)
+	SUBS   $8, len
 	BPL    copyMatchLoop8
 
-	ADD  lenRem, match
+	MOVD (match)(len), tmp2 // match+len == match+lenRem-8.
 	ADD  lenRem, dst
-	MOVD -8(match), tmp2
 	MOVD tmp2, -8(dst)
 	B    copyMatchDone
 
 copyMatchLoop1:
-	// Finish with a byte-at-a-time copy.
-	SUB     $1, len
+	// Byte-at-a-time copy for small offsets.
 	MOVBU.P 1(match), tmp2
 	MOVB.P  tmp2, 1(dst)
-	CBNZ    len, copyMatchLoop1
+	SUBS    $1, len
+	BNE     copyMatchLoop1
 
 copyMatchDone:
 	CMP src, srcend

internal/lz4block/decode_asm.go

@@ -1,3 +1,4 @@
+//go:build (amd64 || arm || arm64) && !appengine && gc && !noasm
 // +build amd64 arm arm64
 // +build !appengine
 // +build gc